Mux blogged about his breakout for the OV9650, all files are available here: I made this breakout for the OV9650 a while ago, and I’ve been waiting to test it before sharing, I finally had the chance to do so, I used an FPGA this time for testing, and here’s the result. The breakout has two SOT23 […]
Tag Archives: FPGA
App note: Using a microprocessor to configure Xilinx FPGAs via slave serial or selectMAP mode
Great app note from Xilinx on configuring their FPGA through slave serial and parallel selectMAP mode This application note describes a technique for configuring an FPGA from an embedded processor. Three common components are required: an embedded microprocessor, some non-volatile memory, and a CPLD. Cost, as well as real estate, can be reduced if the […]
App note: Xilinx in-system programming using an embedded microcontroller
Program Xilinx’ CPLDs and FPGAs with the aid from this app note. By using a simple JTAG interface, Xilinx devices are easily programmed and tested without using expensive hardware. Multiple devices can be daisy-chained, permitting a single four-wire Test Access Port (TAP) to control any number of Xilinx devices or other JTAG-compatible devices. The four […]
Saturn – Another attempt to make open source Spartan 6 FPGA board with DDR SDRAM
Tom of Numato Lab writes: We made a failed attempt to design and build a FPGA development board with DDR SDRAM last year. But this year we tried again and successfully built and tested a Spartan 6 FPGA board with DDR SDRAM. This board was built using KiCad and other open source tools. And best […]
miniSpartan6, another Spartan 6 Kit
The Hardwarer has designed and built this open source FPGA starter kit -miniSpartan6, it is based on Papilio Pro and XuLA2: It is designed around Spartan 6 chip from Xilinx and it has on board JTAG programmer based on FT2232D from FTDI. The miniSpartan6 is built to combine the advantages of both Papilio Pro and XuLA2. It […]
Who says BGA packages are hard to solder
Here is proof that soldering BGA’s is not that hard. Check out this Mandelbrot zoom fractal engine with a PSP display project (machine translation). The FPGA in a ball grid array package is soldered dead bug style. Now that’s skill. Via the forum, and Hack a Day.
Driving an LCD from a broken laptop with an FPGA via the Papilio Plus board
Alex connected up an salvaged laptop LCD to his Papilio Plus FPGA development board. He is designing a pair of boards for easier interface, one is designed as a wing for the dev board, and the other as a breakout for the LCD. They’ll be connected together via an HDMI cable, even though the protocol […]
Precise control of DC motors using an FPGA
Chris wrote extensive documentation on how to implement precise control of DC motors using FPGAs. The goal of this project is to build a simple one input, one output system that will control a motor. The control input will come from a trimpot and the FPGA or CPLD’s job will be to use the input […]
Program Actel FPGAs with the Bus Blaster using DAT files
Mikelelere modified Actel’s DirectC 2.7 programming utility to support the Bus Blaster. With his modifications you should be able to program Actel’s FPGAs using programinn DAT files. The Bus Blaster is a high-speed JTAG debugger for ARM processors, FPGAs, CPLDs, flash, and more. You can get a Bus Blaster v2 for $34.95 at Seeed. Via […]
Pipistrello: Spartan 6 development board with 64MB of RAM, High Speed USB, and HDMI
Magnusk designed the Pipistello Spartan 6 development board with the same IO headers as the Papilio One. It features 64MB of RAM running at 200Mhz, the FDTI FT2232H High Speed USB IC, HDMI output, and a micro-SD card holder. So the only option left was to make my own board – basically merging the FPGA […]
AltOR32: An OpenRISC CPU for small FPGAs
Ultra-Embedded designed a soft core 32bit openRISC CPU with basic ISA functionality for small FPGAs. It fits on the Spartan 3 featured on the Papilio One 250k development board, and comes in pipelined and multi-cycle versions. AltOR32 is an OpenRISC 1000 architecture derived RISC CPU targeted at small FPGAs and contains only the most basic […]
DigitGrid huge display made of multiple 7-segment displays
Skot built a huge display made of many 7-Segment displays that can display animation. It’s driven via an FPGA board.
Camera Wing for Papilio One PCB giveaway at Gadget Factory
Gadget Factory is giving away 8 Papilio One Camera wing PCBs . This can be used with a FPGA and some open VHDL code to display video on a PC. The first 8 people to send an email with a shipping address to support@gadgetfactory.net will get the free PCB’s! (Note: this is a bare PCB […]
FPGACheap DIY Altera FPGA USB programmer
This is a DIY USB programer for Altera FPGAs. It only uses a PIC uC and a few discrete components to provide a JTAG interface with a FPGA. Somun found it on a Japanese site (machine translation), and with the help of Google Translate he built one for himself. There are two versions available. The […]
SID player VHDL core
d18c7db was inspired by Markus’ SID audio file player so he implemented a SID player in VHDL: I spent some time this weekend and got some initial sounds out of my board. I’m using a Papilio FPGA board with a SID core written in VHDL. The sounds coming out sound 90% correct, the tunes are […]
DE0-NANO FPGA development kit review
octal tipped us to a cheap Altera DE0-NANO FPGA Development Kit: …Now most of you will be swayed by cost so lets get that out the way – The DE0-Nano is $79USD and though education routes is only $59USD which I think is really good. Its a little more than the Papilio and XuLA boards […]
Lattice announces Diamond release 1.3
Lattice Semiconductor has just announced Lattice Diamond® release 1.3, updating their FPGA design software environment. They write: This release further builds on helping FPGA designers reach their goals for cost sensitive and low-power applications. In addition to its industry-leading Power Calculator, Lattice Diamond 1.3 software now aids migrating a design to a lower cost device […]
FPGA bitstream security broken
Researchers in Germany have released two papers detailing how security of the bitstream on Xilinx FPGAs can be compromised. The first paper (11 pages) discusses power analysis attacks and extracting keys from Virtex-II devices. The second (3 pages) describes an analysis of the Virtex 4 and 5 bitstream encryption mechanism. Via Slashdot.
Lattice ECP3 FPGA Jamz video
Not content to leave well enough alone with their first humorous video promo for the MachXO2, the people at Lattice Semi released the above video for their Lattice ECP3 family of FPGA devices.
Plunify online FPGA compiler conference call
MP3 download Plunify is an online compiler for Altera and Xilinx CPLDs/FPGAs. The developers’ goal is to build an interface to instant license and computer resources for large FPGA projects. Download the MP3 to hear more about their start-up and some of the difficulties they face with compiler licensing. We’re interested in Plunify because it […]