A detailed guide on designing a CPU in VHDL by Domipheus: This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I’d recommend they are read before continuing. Part 10 was supposed to be a very big part, […]
Steve at Big Mess o’ Wires writes: I finished building my 7400 computer, and posted some demo videos here Via the forum.
Steve at Big Mess o’ Wires posted an update on his Custom 4-Bit CPU: Enough with the vague design talk – here’s the circuit schematic for the Nibbler 4-bit CPU! Click the image to zoom in to a full size view. For simplicity, this version omits some details like bypass capacitors, clock generation, reset circuitry, etc. The […]
Steve at Big Mess o’ Wires writes: I know the Open 7400 Contest is long past, but I wanted to call out a new 7400-based custom CPU I’m building. It’s a 4 bit CPU called “Nibbler”, and more info is on my web site here My goals are to keep the chip count to an absolute […]
Jechavarria has designed and built this DSETA board, a CPU based on the Atmel AT89C51RE2: In my last projects, I always use the same CPU. DSETA board, I say in the posts. Well, here it is, a CPU based on the AT89C51RE2 microcontroller from Atmel. I develop this board for some reasons. The first and […]
Ultra-Embedded designed a soft core 32bit openRISC CPU with basic ISA functionality for small FPGAs. It fits on the Spartan 3 featured on the Papilio One 250k development board, and comes in pipelined and multi-cycle versions. AltOR32 is an OpenRISC 1000 architecture derived RISC CPU targeted at small FPGAs and contains only the most basic […]