Program Xilinx’ CPLDs and FPGAs with the aid from this app note.
By using a simple JTAG interface, Xilinx devices are easily programmed and tested without using expensive hardware. Multiple devices can be daisy-chained, permitting a single four-wire Test Access Port (TAP) to control any number of Xilinx devices or other JTAG-compatible devices. The four mandatory signals comprising the JTAG TAP are: Test Clock (TCK), Test Mode Select (TMS), Test Data Input (TDI), Test Data Output (TDO)The processor and JTAG chain schematic shown above can help designers achieve these unprecedented benefits by providing a simple means for programming Xilinx CPLDs and FPGAs from design information stored in the embedded processor memory space. This design can be modified for remote downloading applications and the included reference C code can be compiled for the designer’s processor of choice.