Reverse-engineering the first FPGA chip, the XC2064

Ken has written an article on reverse engineering the first FPGA chip, the XC2064: The FPGA was invented by Ross Freeman1 who co-founded Xilinx2 in 1984 and introduced the first FPGA, the XC2064. 3 This FPGA is much simpler than modern FPGAs—it contains just 64 logic blocks, compared to thousands or millions in modern FPGAs—but […]

APP NOTE: make an analog to digital converter using FPGA pins

A differential pin pair can be used as a comparator to create a basic ADC. This app note shows how to design a low speed (1 KHz) and “high” speed (50 Khz) ADC technique using only FPGA pins, a resistor and a capacitor. Regardless of whether we ever use this technique, it is illuminating to […]

BUS PIRATE: pipelined and non-pipelined commands

Bus Pirate prototype Ultra v1b uses an FPGA to process commands sent through a FIFO buffer to a state machine. Pipelined commands can be loaded into the FIFO and executed by the state machine with per-clock repeatability. Non-pipelined commands halt the state machine while the MCU takes over to perform the command, the delay is […]

App note: FPGA power supply considerations

App note from Vishay Siliconix, giving us tips on powering FPGAs. Link here (PDF) An FPGA is a device that offers many logic elements – up to 1 million gates in a single device at this writing – as well as other functionality such as transceivers, PLLs, and MAC units for complex processing. FPGAs are […]

PROTOTYPE: Bus Pirate “Ultra” v1b

Today we finished stuffing the first Bus Pirate “Ultra” v1b board. This includes the updates we posted this week, and a few other improvements from v1a: 8 general purpose IO pins 0.8-5.0volt programmable power supply Voltage measurement on all 8 IO pins Pull-up resistors on all pins, fed from Vout/Vref pin Display connector USB C […]

PROTOTYPE: Bus Pirate/Logic Analyzer with Ice40 FPGA

Bus Pirate “Ultra” taps an iCE40 FPGA to power a combined Bus Pirate interface and logic analyzer that is infinity hackable. Previous Bus Pirates relied on the hardware peripherals available in a microcontroller, which vary in features and have the occasional bug. With an FPGA we can implement practically any peripheral with all the fixes […]

BML USB 3.0 FPGA interface over PMOD

An open-source-hardware USB 3.0 to FPGA PMOD interface design from Black Mesa Labs: Black Mesa Labs is presenting an open-source-hardware USB 3.0 to FPGA PMOD interface design.  First off, please lower your expectations. USB 3.0 physical layer is capable of 5 Gbps, or 640 MBytes/Sec. This project can’t provide that to your FPGA over 2 […]

BML HDMI video for FPGAs over PMOD

Here are two open-source-hardware HDMI  video boards for adding digital video to FPGA platforms with standard PMOD connectors from Black Mesa Labs: The BML 3bit HDMI over single-PMOD uses 7 of 8 available LVCMOS 3.3 pins on a single PMOD to provide 3bit color ( R,G,B 100% On or Off ). Example Verilog design drives 800×600 […]

App note: Choose the right power supply for your FPGA

Designing a power supply for FPGA includes multiple voltage, ripple management and power sequencing, here’s an app note from Maxim Integrated. Link here (PDF) Field-programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs) require 3 to 15, or even more, voltage rails. The logic fabric is usually at the latest process technology node that […]

App note: Clearing Xilinx FPGA configuration to allow boundary scan testing

Another application note from XJTAG on preparing Xilinx FPGA for proper boundary scan testing. Link here When Xilinx FPGAs are configured it can restrict the boundary scan access to some signals on the device. One work-around for this problem is to configure the FPGA with a ‘blank’ image that closely matches its unconfigured state, allowing […]

App note: Active capacitor discharge circuit considerations for FPGAs

Power down sequencing and discharging on FPGAs app note from Diodes Incorporated. Link here (PDF) FPGA’s need the different power rails to be powered up and down in a defined sequence. For power down, each sequenced rail needs to be fully off before the next rail is turned off. With large high speed and high […]

A FPGA controlled RGB LED MATRIX for Incredible Effects – the Hardware

Boris Landoni from Open Electronics writes: In this post you will find  the description of a graphic display that uses a modular solution based on dot matrix blocks (in which each dot is a RGB LED), that are driven – via a specific bus – by a very powerful control board, that is entirely programmable […]

Old, not obsolete. Working with the Xilinx Virtex-E FPGA in a huge BGA package

Andy Brown not only did a nice write up about his experience with the Xilinx XCV600e FPGA and creating a development board for it, but he also did a great video walkthrough: The general aim of this project will be to create a generic development board for the FPGA. This isn’t as simple as it […]

Nanocounter is an accurate frequency counter using an FPGA, STM32 and a bluetooth android app

Andy Brown has designed and built a frequency counter using an FPGA, STM32F072 and an Android GUI – the Nanocounter: After studying the above counting methods I decided on the following goals for my frequency counter, which I’m going to call Nanocounter. Very accurate measurement over a range of 1 to 50MHz. This would cover the range […]

How do I FPGA?

TC-Engineering writes: I’ve been thinking about building stuff with FPGA’s for a while, and usually get turned away because FPGA’s are considerably harder to implement than microcontrollers since they have no on-chip memory. It is necessary to re-program the gates every time they power up, which requires an external flash memory chip. There aren’t great […]

Mesa-Video: 800×600 digital video for Arduinos over 2-wire serial Mesa-Bus

kevinhub88 writes: This post describes Mesa-Video, a low cost, low power, small size and fully Open Source Hardware and Software solution for providing 800×600 digital video for Arduino ( and other ) microcontrollers.  Mesa-Video makes it quick and easy to display text and 24bit color graphics from any MCU using a single UART serial port […]

App note: Implementing a TMDS video interface in the Spartan-6 FPGA

Implementing a TMDS video interface in the Spartan-6 FPGA, an app note here (PDF!) from Xilinx: The DVI and HDMI protocols use TMDS at the physical layer. The TMDS throughput is a function of the serial data rate of the video screen mode being transmitted. This in turn determines the FPGA speed grade that must be used to […]

Announcing the STREAM board

The Myriad crew  has announced the new Stream board released through the MyriadRF initiative for doing SDR with the LMS6002D/LMS7002M from Lime Microsystems. It’s a fully Open Source board with Kicad design files and a fully Open Source OpenRISC SoC for the FPGA: We are thrilled to announce that the STREAM board is the latest project […]

App note: FPGA configuration from SPI Flash memory using a Microprocessor

From Xilinx application note on FPGA configuration method: This application note describes a simple and efficient FPGA configuration method that utilizes a microprocessor to configure an FPGA device from a Serial Peripheral Interface (SPI) flash memory. This method reduces hardware components, board space, and costs. Reference hardware design and firmware are included to illustrate the methodology.

PyroElectro: Who can build the best P-O-V contest

PyroElectro is currently running a contest for who can build the best handheld or spinning POV device using an FPGA or CPLD. They’ll be presenting an example POV using VHDL in Lesson 9 @ PyroEdu. The top prize is a Basys2 Spartan-3E FPGA board valued at roughly $90.00.   Visit PyroElectro POV contest page for more […]