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Posts Tagged ‘Xilinx’

Old, not obsolete. Working with the Xilinx Virtex-E FPGA in a huge BGA package

Wednesday, July 13th, 2016

Andy Brown not only did a nice write up about his experience with the Xilinx XCV600e FPGA and creating a development board for it, but he also did a great video walkthrough: The general aim of this project will be to create a generic development board for the FPGA. This...

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Posted in FPGA | 5 Comments »

App note: QuickBoot method for FPGA design remote update

Sunday, January 31st, 2016

A QuickBoot method for FPGA design remote update application note (PDF!) from Xilinx: This application note presents detailed descriptions of the QuickBoot method that are important for evaluating the QuickBoot solution and debugging implementation problems. Demonstration implementations of the QuickBoot method are provided for the KC705 evaluation board using the serial...

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App note: Isolation design flow for Xilinx 7 series FPGAs or Zynq-7000 AP SoCs (ISE Tools)

Saturday, September 26th, 2015

Xilinx application note, Isolation design flow for Xilinx 7 series FPGAs or Zynq-7000 AP SoCs (ISE Tools) (PDF!) This application note is written for FPGA designers wishing to implement security or safety critical designs, that is, information assurance (single chip cryptography), avionics, automotive, and industrial applications, using the Xilinx Isolation Design Flow...

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App note: Zero Latency Multiplexing I/O for ASIC Emulation

Saturday, September 5th, 2015

Zero Latency Multiplexing I/O for ASIC Emulation (PDF!) application note from Xilinx: This application note provides a method for FPGA emulation platforms to communicate multiple signals over one I/O or I/O differential pair to another FPGA. This multiplexing method serializes data up to 800 Mb/s without introducing any additional cycles...

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App note: Implementing a TMDS video interface in the Spartan-6 FPGA

Saturday, June 20th, 2015

Implementing a TMDS video interface in the Spartan-6 FPGA, an app note here (PDF!) from Xilinx: The DVI and HDMI protocols use TMDS at the physical layer. The TMDS throughput is a function of the serial data rate of the video screen mode being transmitted. This in turn determines the FPGA speed grade...

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App note – Power distribution system (PDS) design: Using bypass/decoupling capacitors

Saturday, May 9th, 2015

An app note (PDF!) from Xilinx on power distribution system (PDS) design using bypass/decoupling capacitors: This application note specifies how to build power distribution systems for Virtex™ devices. It also covers the basic principles of power distribution systems and bypass or decoupling capacitors. A step-by-step process is described where a power...

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App note: Designing efficient digital up and down converters for narrowband systems

Saturday, March 21st, 2015

An app note (PDF!) from Xilinx on designing efficient digital up and down converters for narrowband systems: Digital Up Converters (DUC) and Digital Down Converters (DDC) are key components of RF systems in communications, sensing, and imaging. This application note demonstrates how efficient DUC/DDC implementations can be created by leveraging Xilinx® DSP...

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App note: D-PHY Solutions

Saturday, March 7th, 2015

An app note (PDF!) from Xilinx on D-PHY Solutions: Traditionally, interfaces between components on a printed circuit board (PCB) are based on single-ended parallel buses at low bit rates (LVCMOS), differential high-speed serial buses, or single differential channels. The D-PHY provides an extension to this structure by turning the low-speed, low-power interface to the...

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Posted in app notes | 1 Comment »

App note: FPGA configuration from SPI Flash memory using a Microprocessor

Saturday, January 31st, 2015

From Xilinx application note on FPGA configuration method: This application note describes a simple and efficient FPGA configuration method that utilizes a microprocessor to configure an FPGA device from a Serial Peripheral Interface (SPI) flash memory. This method reduces hardware components, board space, and costs. Reference hardware design and firmware are...

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Posted in app notes | 1 Comment »

App note: AXI Chip2Chip reference design for real-time video

Saturday, October 25th, 2014

AXI Chip2Chip reference design for real-time video application (PDF!) from Xilinx: The LogiCORE™ IP AXI Chip2Chip is a soft Xilinx core that provides bridging between Advanced eXtensible Interface (AXI) systems for multi-device System-On-Chip solutions. This application note provides a setup demonstrating real-time video traffic across Kintex®-7 FPGA and Zynq®-7000 All Programmable (AP)...

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App note: Power-supply solutions for Xilinx FPGAs

Sunday, October 19th, 2014

MAXIM's power solution for Xilinx' FPGAs. App note here (PDF!) Field-programmable gate arrays (FPGAs) are used in a wide variety of applications and end markets, including digital signal processing, medical imaging, and high-performance computing. This application note outlines the issues related to powering FPGAs.  

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App note: Driving LEDs with Xilinx CPLDs

Sunday, February 16th, 2014

Here's Xilinx app note on using CPLDs to perform the same functionality as those common LED driver chips. Light-Emitting Diodes (LEDs) are commonplace on the modern day Printed Circuit Board (PCB). Whether they are indicating status, activity or some other function, they need to be driven by a device that...

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Posted in app notes | 1 Comment »

App note: Using a microprocessor to configure Xilinx FPGAs via slave serial or selectMAP mode

Sunday, February 16th, 2014

Great app note from Xilinx on configuring their FPGA through slave serial and parallel selectMAP mode This application note describes a technique for configuring an FPGA from an embedded processor. Three common components are required: an embedded microprocessor, some non-volatile memory, and a CPLD. Cost, as well as real estate,...

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Posted in app notes | 7 Comments »

App note: CPLD timing

Sunday, January 5th, 2014

See from Xilinx app note the timing constraints on CPLDs. In this application note we will discuss how to constrain a CPLD design and how to verify that the design has met timing. Fundamentally, CPLD timing is the same as FPGA timing; however, the CPLD timing constraints are a subset...

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App note: Understanding XC9500XL CPLD power

Sunday, January 5th, 2014

Here's an app note from Xilinx on calculating power consumption for a CPLD. The goal of this application note is to discuss XC9500XL CPLD power estimation and optimization and provide the reader with an understanding of sense-amplifier based CPLD power dissipation. A brief discussion of the process for estimation is...

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App note: CPLDs as Motor Controllers

Saturday, January 4th, 2014

Here's a simple motor controller implementation using CPLDs from Xilinx. To enable a CPLD to turn the electromagnets on and off, external transistor drivers must be used. A unipolar stepper motor can be driven by four identical NPN or N-channel drive transistors. The various Xilinx CPLDs can operate with I/O...

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App note: Xilinx in-system programming using an embedded microcontroller

Saturday, January 4th, 2014

Program Xilinx' CPLDs and FPGAs with the aid from this app note.By using a simple JTAG interface, Xilinx devices are easily programmed and tested without using expensive hardware. Multiple devices can be daisy-chained, permitting a single four-wire Test Access Port (TAP) to control any number of Xilinx devices or other...

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Posted in app notes | 2 Comments »

Xilinx CPLD design techniques online documentation

Monday, December 3rd, 2012

Xilinx has an online searchable database of information on programming their CPLD devices. It includes a number of cool tips and code samples for implementing bidirectional signals, clock dividers, global nets as well as information on CPLD attributes, the schematic library and controlling I/O pin voltages. In many cases code...

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Posted in CPLD, documentation | No Comments »

3D Model: XC95144XL Breakout Board

Monday, June 18th, 2012

Today we made the 3D model of the XC95144XL CPLD breakout board. The board has 39 of the CPLD pins broken out to a "Blade" style configuration, while the remaining  pins are broken out to two dual-row headers featured on top corners of the board. Check out our tutorial on...

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Programing CoolRunner II CPLDs from Windows 7

Monday, April 2nd, 2012

[embed]http://www.youtube.com/watch?v=z7sX88A48IY&feature=player_embedded[/embed] Kiran wrote a short tutorial on how to program the Xilinx CoolRunner II CPLD development board with a computer running Windows 7.  The board features an onboard USB programmer but the drivers for it are not supported by Windows 7. The only way to program the device, without buying...

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Posted in how-to | 5 Comments »

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