Lattice announces Diamond release 1.3

Posted on Tuesday, July 26th, 2011 in CPLD, FPGA, software by the machinegeek

Lattice Semiconductor has just announced Lattice Diamond® release 1.3, updating their FPGA design software environment. They write:

This release further builds on helping FPGA designers reach their goals for cost sensitive and low-power applications. In addition to its industry-leading Power Calculator, Lattice Diamond 1.3 software now aids migrating a design to a lower cost device as well as improving design resilience with clock jitter analysis. Other new software enhancements include support of complex multi-file simulation testbenches, a more intuitive synthesis constraint flow, and a significant speed-up of the download of large trace data and complex trigger configuration for on-chip debugging.

You can download your copy (1.8 GB) from the Lattice website.

This entry was posted on Tuesday, July 26th, 2011 at 7:40 pm and is filed under CPLD, FPGA, software. You can follow any responses to this entry through the RSS 2.0 feed. You can skip to the end and leave a response. Pinging is currently not allowed.

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