Category Archives: CPLD

Free online course: basics of programmable logic

Altera has available a free online course covering the Basics of Programmable Logic. This training will give you a basic introduction to programmable logic devices, focusing on FPGAs. By exploring the history of programmable logic technologies, you’ll learn about the architectural features that make up an FPGA device. You will see the advantages of using […]

App note: CoolRunner-II character LCD module interface

Xilinx has an application note explaining how to use LCD modules with a CPLD. CoolRunner-II CPLDs can be used to control dot-matrix liquid crystal display (LCD) modules. The low-power characteristics of LCD modules make them an ideal complement to the CoolRunner-II family. These displays typically require 3.3V signals. However, this is not of concern because […]

CPLD FLASH memory write cycles

All components using rewritable memory have a finite limit on the number of program/erase cycles they are specified to endure. Researching this issue yields the following data in regard to CPLD memory write cycle specs: Xilinx XC9572XL 10,000 Xilinx Coolrunner-II XC2C64A 1,000 Altera’s Max V CPLD 1,000 Altera’s Max 3000A/7000 100 Lattice Semi MachXO2 100,000 […]

Lattice announces Diamond release 1.3

Lattice Semiconductor has just announced Lattice Diamond® release 1.3, updating their FPGA design software environment. They write: This release further builds on helping FPGA designers reach their goals for cost sensitive and low-power applications. In addition to its industry-leading Power Calculator, Lattice Diamond 1.3 software now aids migrating a design to a lower cost device […]

3 wire DLG2416 CPLD display controller

Alan posted this project at FromOrbit demonstrating how to implement three wire control of a DLG2416 display using a CPLD. The chip he chose was the Xilinx XC9536 which is the 36 macrocell version of the XC9572 CPLD found in our CPLD Development Board, so this can be implemented on our board with room to […]

Plunify online FPGA compiler conference call

MP3 download Plunify is an online compiler for Altera and Xilinx CPLDs/FPGAs. The developers’ goal is to build an interface to instant license and computer resources for large FPGA projects. Download the MP3 to hear more about their start-up and some of the difficulties they face with compiler licensing. We’re interested in Plunify because it […]

New release: XILINX ISE Design Suite 13.2

Xilinx has announced the availability of their ISE Design Suite 13.2. While most of the improvements appear geared toward the 7 Series FPGA families, if you’re in need of the Xilinx software or just want to upgrade you’ll find downloads for Windows and Linux here. As a much appreciated courtesy, Xilinx is also making DVDs […]

One step XSVF file generation for CPLD

If you’re using one of our CPLD Development Boards you need to have a file in XSVF format to download to the board using the Bus Pirate loaded with the BPXSVFPLAYER firmware. We’ve posted a method to convert SVF files to XSVF format, but Xilinx has included a handy way to produce “One Step XSVF” […]

Plunify interview questions

Tomorrow we’re talking with Plunify, the developers of an online compiler for Altera and Xilinx CPLDs/FPGAs. They added the CPLD dev-board demos to a list of project examples, and made a tutorial video. We put together a how-to when we tested it. Unfortunately, Xilinx has not yet given Plunify permission to use the compiler in […]

Lattice launches “Do-It-All PLD” design challenge

Lattice Semiconductor Corporation and UBM Electronics have announced the Lattice “Do-it-All PLD” Design Challenge. The objective of the Design Challenge is to foster a social community in which electronics engineering contestants can use the Lattice MachXO2™ Pico Development Kit to create designs for evaluation by a panel of expert judges. The Design Challenge will take […]

Tiny CPU: testbed for CPLD-based processors

Tiny CPU uses an Altera CPLD to emulate a simple processor. Also included on the board: flash ROM, keyboard input, JTAG header, and more. Tiny CPU is a custom “small CPU” design intended for implementation in a CPLD. Such soft CPU cores typically target an FPGA or large CPLD, but the target device for Tiny […]