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Posts Tagged ‘board layout’

App note: Best design and layout practices for SiTime oscillators

Sunday, June 19th, 2016

SiTime's app note about how to properly route an oscillator's PCB traces. Link here Proper decoupling, bypassing, and power supply noise reduction is important in many applications to ensure optimal performance for oscillators. A common strategy is to place capacitors near high speed devices on a printed circuit board (PCB)....

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App note: Board layout tips for switchmode DC/DC converters

Saturday, October 15th, 2011

The app note featured here provides basic PCB layout tips for building switch-mode DC/DC converters. As an integral part of their function, switch mode converters have square like signals in some of their traces. These signals create harmonics from the switching frequency that can cause much EMI interference, as well as...

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Tiny CPU: testbed for CPLD-based processors

Friday, June 10th, 2011

Tiny CPU uses an Altera CPLD to emulate a simple processor. Also included on the board: flash ROM, keyboard input, JTAG header, and more. Tiny CPU is a custom “small CPU” design intended for implementation in a CPLD. Such soft CPU cores typically target an FPGA or large CPLD, but...

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Posted in CPLD, dev boards | 3 Comments »

Recent Comments

  • Drone: So these go for around $330 USD and NO published calibration procedure online or otherwise? Given what's inside - I don't think I'll be considering...
  • Pekka Akselin: This is ridiculous!? :-) We are back at 256(!) byte EPROMs that needed multiple, a handful, of voltages to run! :-(
  • KH: Let's try a back-of-envelope calc balancing energies. From MCP1700 datasheet, there are graphs for a 200mA load step. Estimate the energy shortfall as 12uJ. Say...
  • Daniel: It's been a week and my comment is still awaiting moderation. Apparently the CIA doesn't want their involvement known?
  • KH: Agree, so okay, I guess he must have learned from somewhere. 100nF and 1000uF is so far apart, that was jarring; it's more magic incantation...