Category Archives: CPLD

CPiLD: CPLD board for Raspberry Pi

Brian designed a CPLD expansion board for the Raspberry Pi. It features a Xilinx XC9572 CPLD, and a i2c buffer connected to Raspberry Pi’s GPIO pins, and I2C port. It is designed to extend R-Pi’s GPIO, and allow for easy solderless bread board prototyping. CPiLD allows for easy breadboarding with fewer wires as it can […]

ADS-B sync and Manchester decoding in CPLD

P. Kusmierski posted an article on flipthatbit describing ADS-B sync and Manchester decoding in CPLD. The CPLD used is a Xilinx XC9536XL (which is the smaller version of the XC9572XL found in our CPLD Development Board.) Having put together my miniADSB I needed to extract the actual data from the Manchester encoded bit streams it […]

Verilog project: Binary to 7-segment display

DJ Delorie was looking for an excuse to learn about Verilog and CPLDs. So he coded up this binary to 7-segment display converter. He provides links to the source code and says this project fits into the Xilinx XC9572 (the same chip used in our Coolrunner-II CPLD breakout board. You can get our XC9572XL dev-board […]

Free Model Foundry: open source CPLD/FPGA simulation models

Here’s a site we found containing open source simulation models for system level verification of CPLD/FPGA devices. “Founded in 1995, Free Model Foundry (FMF) is dedicated to promoting standard modeling practices within the electrical engineering comunity. In particular, we support the use of VHDL, Verilog, and SystemVerilog modeling languages. They believe in free, open source […]

Xilinx free online Xcell Journal

Xilinx has released Issue 78 of Xcell Journal, their free online publication for embedded system and programmable logic developers. Each issue of Xcell has articles targeted at developers from every skill level, from beginner to expert. You can check out individual articles from this issue or download past issues back to 1988 at the Xilinx […]

CPLD breakout board ported to KiCad

Numanto Lab ported one of our CPLD breakout boards from the original Eagle files to the open source KiCad. CPLD breakout board design in KiCad based on design by Ian Lesnet of Dangerous Prototypes. This board is completely designed in KiCad in 3-4 hours. Get the CoolRunner-II development board for $15 and XC9572XL dev-board  for […]

Xilinx ISE Design Suite v 13.4 now available

Xilinx has announced the availability of Version 13.4 of their ISE Design Suite. This download includes the free Webpack version of the ISE and is available for Windows and Linux. This release introduces their new MicroBlaze Micro Controller System (MCS), making a MicroBlaze-based processing system available in the ISE WebPACK edition. This is the software […]

VHDL communication with a PS/ 2 keyboard

Hamster has written VHDL code for interpreting data from a PS2 keyboard. It’s currently a work in progress and is designed to work with his Papilio S6 (the Spartan 6-based Papilio board paired with the Megawing board, both available from Seeedstudio.) The code receives the scancode from a PS2 keyboard attached to Port A of […]

ALSE free IP cores for non-commercial CPLD/FPGA dev

Advanced Logic Synthesis for Electronics (ALSE) is a Paris based company providing product development, IP consulting and training courses involving HDL, ASIC and FGPA devices. They are making available a series of IP cores free for personal, non-commercial use. They state: For non-commercial projects only, we have taken the decision to offer some functions for […]

NBW-SDR: NBitWonder software defined radio

NBitWonder writes: Over at NBitWonder, we have been working to develop a software-defined radio for a few months. Last weekend, the radio received its very first signals. There is a short writeup and demonstration video at our website. This is quite similar to Jeri Ellsworth’s design in that is uses a Tayloe detector and some […]

Thursday Project: XC95144XL CPLD breakout board PREVIEW

After Jason shared his design of a XC95144XL breakout board, we made our own breakout for the same chip. It features a single row of 39 pins that can be interfaced with a standard bread board. All the remaining pins are broken-out to dual-row headers on top of the board. A 800mA 3.3V voltage regulator […]

Xilinx ISE Design Suite v 13.3 now available

Xilinx has announced the availability of Version 13.3 of their ISE Design Suite. This download includes the free Webpack version of the ISE and is available for Windows and Linux. This is the software package used to develop for our CPLD Development Boards. Don’t want to download 4.9 GB? No problem. Xilinx is making the […]

XC9572XL breakout board: Frequency counter

Jason implemented a frequency counter on an XC9572XL CPLD. It uses a 1Mhz clock to count the duration of the input signal pulse, and shows the output on a 6 digit display. Initially he had to use additional 7400 logic ICs to convert BCD output from the CPLD to the 7-segment displays. With some tweaking […]

Openschemes homebrew SVF player

Openschemes has a tutorial describing their project for bit bang JTAG programming of Xilinx CPLDs using their homebrew SVF player. They describe: Today’s lesson consists of the development of a bit-banged JTAG SVF player in order to program a device such as a CPLD. It’s quite likely that the SVF player we develop today could […]

8-bit CPLD graphics card using XC9572

Ulrich Radig from Germany has developed an 8-bit graphics card based on the XC9572 CPLD. In addition to the CPLD chip (the same one used in our CPLD dev board), he added two cache blocks from an old motherboard. (He reports that the SRAM chip CY7C199-15 could be used instead.) He states, “[t]he graphics card […]