Categories

Plunify interview questions

Posted on Thursday, June 30th, 2011 in CPLD, FPGA, interviews by Ian

Tomorrow we’re talking with Plunify, the developers of an online compiler for Altera and Xilinx CPLDs/FPGAs. They added the CPLD dev-board demos to a list of project examples, and made a tutorial video. We put together a how-to when we tested it.

Unfortunately, Xilinx has not yet given Plunify permission to use the compiler in this fashion, so the tutorial cannot go live for the moment… We’ll talk to them about that happened, and ask your questions too.

Please post questions in the comments below, or in the forum.

This entry was posted on Thursday, June 30th, 2011 at 1:59 pm and is filed under CPLD, FPGA, interviews. You can follow any responses to this entry through the RSS 2.0 feed. You can skip to the end and leave a response. Pinging is currently not allowed.

Leave a Reply

Notify me of followup comments via e-mail. You can also subscribe without commenting.

Recent Comments

  • Craig B: Shouldn't the default be 00xxx010? Note that bit 0 appears out of order in the documentation. In that case I think the initial value is...
  • JJM: From the datasheet extract you are showing, the power up status should be 00xxx010, not 000xxx01. Bit numbering is misleading since 'measurement resolution' is apparently...
  • Jan Ciger (@janoc200): Hmm, that could actually explain why the three sensor IMU breakout I have bought a few years ago had all sorts of issues - I...
  • Travis: Is it preset to the windows 3 fingered salute?
  • Glenn: What a cool idea !