The HDL is complete enough to start testing on real hardware. This update puts almost every feature under control of the state machine in the FPGA so commands can be pipelined with repeatable precision. Commands (write/read SPI, set/clear pin, measure voltage, update PWM, enable pull-up resistors, etc) are pushed into a FIFO buffer using a […]
Tag Archives: Verilog
FPGA : RC Servo and Stepper motor control in Verilog
Trandi blogged about his RC servo and stepper motor project. He writes: For those interested in reproducing this example: The board is called “EP2C5 Mini Board” and has a EP2C5T144C8 Cyclone II FPGA on it I used a standard, 9grams micro RC Servo I used a 28BYJ-48 stepper motor and it’s driver (you can purchase these […]
NandLand – FPGA info and tutorial site
Russell is interested in working with FPGAs. He’s developed an educational website: www.nandland.com. “It’s an educational website for people interested in learning about FPGAs and ASICs, mostly by focusing on VHDL and Verilog tutorials and examples. I have written all of the content on it myself and I’m adding new content constantly.” Check it out! […]
Building a CPLD based logic analyzer
Alex from InsideGadgets has been working on a Building a CPLD Based Logic Analyser. In Part I of his post he details his build of a logic analyzer which saves the sample to external SRAM. For this project Alex used the Altera MAXII EPM240 development board with an on board 20MHz oscillator. The coding was […]
Hand-tracking Anti Tetris game on DE2 board
Tian Gao from Cornell’s University’s EE program developed what he calls an AntiTetris game using the Altera DE2 FPGA board. The project was part of the final requirements in Cornell’s ECE 5760 Advanced Microcontroller Design and system-on-chip Spring 2013 course. “In this project, I built a video game “Anti Tetris” on Altera DE2 board. The […]
Homebrew Cray-1A on Xilinx Spartan-3E board
Chris Fenton has spent the last year and a half or so constructing his own 1/10-scale, binary-compatible, cycle-accurate Cray-1. He says this project falls purely into the “because I can!” category.” The actual design was implemented in a Xilinx Spartan-3E 1600 development board. For vintage computing enthusiasts, Chris also provides an interesting link to the […]
Verilog project: Binary to 7-segment display
DJ Delorie was looking for an excuse to learn about Verilog and CPLDs. So he coded up this binary to 7-segment display converter. He provides links to the source code and says this project fits into the Xilinx XC9572 (the same chip used in our Coolrunner-II CPLD breakout board. You can get our XC9572XL dev-board […]
Free Model Foundry: open source CPLD/FPGA simulation models
Here’s a site we found containing open source simulation models for system level verification of CPLD/FPGA devices. “Founded in 1995, Free Model Foundry (FMF) is dedicated to promoting standard modeling practices within the electrical engineering comunity. In particular, we support the use of VHDL, Verilog, and SystemVerilog modeling languages. They believe in free, open source […]
Understanding Verilog warnings
Big Mess o’ Wires has a review of Verilog warnings: Those of you who’ve followed the blog for a while know about my many frustrations with Verilog. Because it feels sort of a like a procedural programming language, but very definitely isn’t one, I keep expecting to be far more competent at Verilog design than […]
MCPU – minimal CPU on a CPLD
Here’s a project from opencores by Tim Boscke known as MCPU. It creates a minimal CPU on a CPLD with at least 32 macrocells (such as our XC9572 CPLD Dev Board with 72 macrocells.) Tim describes: MCPU is a minimal cpu aimed to fit into a 32 Macrocell CPLD – one of the smallest available […]
Verilog model for 24xx1025 EEPROM released
octal writes: Microchip released the Verilog model for 24xx1025 Devices :) a good learning experience Via the forum.
Simple CPLD binary counter project
FlipThatBit released this video of a simple CPLD binary counter project. This is a good beginner’s Verilog project, requiring a minimum number of external components, and providing an immediate visual result of your efforts. This was written for the XC9536XL CPLD on a homemade project board. It should work just fine on our XC9572XL Development […]
Implementation of UART transmitter in Verilog HDL for Spartan3 FPGA
If you’re experimenting with FPGAs its helpful to know how various common tasks are coded. Here is an article by M. Yasir explaining how to code a UART transmitter in a Spartan 3 FPGA. The tutorial uses the Verilog hardware definition language.
PLUNIFY: programmable logic design simplified
A new site allows you to conduct programmable logic design with Xilinx and Altera devices “in the cloud.” PLUNIFY, currently in Beta, allows you to experiment with PLD development in your web browser without downloading any software. A free account is available allowing you to 1 GB of storage space and free online development tools […]