Category Archives: logic analyzer

NEW PROTOTYPE: Logic Shrimp logic analyzer

The Logic Shrimp is a medium speed, low-cost logic analyzer with a USB interface. It can capture up to 256K samples at 20MHz, and is compatible with the open source SUMP logic analyzer client. The 23K256 serial SRAM from Microchip makes this project possible. Each chip stores up to 256K samples from one logic analyzer […]

Logic Sniffer advanced trigger support

flubberlab is diagramming the advanced triggers in the new Logic Sniffer Demon core in hopes of adding software support in the client. To understand the trigger system, and with an eye toward a trigger configuration user-interface (and application perhaps), I attempted to flesh-out the trigger resource and sequence illustrations shown in the OLS FPGA specification […]

Alternative Logic Sniffer client v0.9.4 RC1

A release candidate of Jawi’s Logic Sniffer client is available for beta testers. It took longer than originally anticipated, but it is finally available: the first Release Candidate (RC) of the 0.9.4 version! Implemented features and issues solved in this release: VCD exports ignore selected channel groups Verify frequency measurement with RLE captures Support OLS-device […]

Arduino logic analyzer with Logic Sniffer client

gillham wrote a logic analyzer firmware for the Arduino that works with on the Logic Sniffer client: Reading through the SUMP docs the protocol looked simple enough that I thought “Why not try implementing this on the Arduino?” and set about it. After getting my code to respond appropriately and kind of working with the […]

Logic Sniffer: 3.07 Demon core release

There’s a new one-stop shop for the Logic Sniffer at Gadget Factory, with Linux and Windows update packages containing the latest 3.07 releases: OpenBench Logic Sniffer Version 3.07 is now available for download at the new Logic Sniffer information portal. For more information take a look at the Release Notes. This release was generated with […]

Logic Sniffer: Updated VHDL code and continous sampling mode

While we all followed dogsbody’s work on the new Verilog Demon Core for the Logic Sniffer, kinsa cleaned up the old VHDL core: New SPI code, works with the latest PIC firmware (v3.0) Working Metadata command New RLE code; n bit counters for n bit data width (except for 24 bits). Additional compression for cases […]

Logic Sniffer: Demon Core v3.07 and firmware updates

Dogsbody released Demon Core v3.07 for the Logic Sniffer with the following fixes: Fixes problem with demux DDR captures causing bogus glitches Fixes missed samples when armed. Ensures the finish-now command works cleanly Minor tweaks to the adv-trigger. A full spec Note: Please be sure to use Jawi’s 0.9.3 release (or newer)! We released an […]

Wanted: Dedicated Logic Sniffer test squad

Development on the Logic Sniffer client is blazing forward. Jawi, and a few new contributors, are adding features daily. The development team is looking for a few dedicated beta testers on various platforms. The squad will test whether a pending release is functioning properly on Windows, Linux, and Mac OS, before it goes live. If […]

Logic Sniffer: Demon Core v6

Dogsbody released v6 of the Verilog core for the Logic Sniffer, codename “Demon Core”. Try it with Jawi’s latest 0.9.3.1 client software: Feb 8 Edit: Release6. Removed inclusive-RLE mode, since breaks older clients and is no longer used by Jawi’s. Also fixed 24-bit RLE counts. Note: Please be sure to use Jawi’s 0.9.3 release (or […]

Logic Sniffer: 3.06 Demon Core test

The Gadget Factory has a complete upgrade package for the new v3 Logic Sniffer core and firmware: Here is a package that eliminates the hassle of getting up and running with the latest “Demon” Core. Included is Jawi’s latest client and an upgraded version of the OLS Upgrader. The OLS Upgrader will step you through […]

Logic Sniffer: Windows GUI upgrade utility

dogsbody released a new version of his Windows GUI upgrade utility for the Logic Sniffer. It now upgrades both the PIC microcontroller an the FPGA ROM chip: I’ve updated my Windows GUI OLS loader to support programming PIC firmware. There are no extra knobs or buttons needed. Just select an image file, and the loader […]

Logic Sniffer important bug fix firmware v2.5

There is a new firmware v2.5 for the Logic Sniffer with an important bug fix. Please upgrade your Logic Sniffer right away. We noticed a bug in the OLS firmware where the PIC and FPGA could both try to control the ROM CS pin at the same time during the self-test. Firmware v2.5+ fixes this […]

Alternative Logic Sniffer client v0.9.3

Jawi has a new version of his client for the Logic Sniffer. This supports new features in the experimental Verilog core from dogsbody. Download it here. Here’s the major updates, see the changelog for more: RLE routines are heavily updated to match the latest firmwares of rasmus and IED/dogsbody. Now supporting 8, 16, 24 and […]

How-to use OLS to debug fpga

Jack Gassett put together a series of videos, at The Gadget Factory demonstrating how to debug the internal logic of an fpga using the open workbench logic sniffer. “When I was debugging the UART communications last week I discovered a new way to debug internal FPGA logic. I put together a screencast for those who […]

All new Logic Sniffer FPGA core

dogsbody rewrote the entire Logic Sniffer FPGA core in Verilog and added nearly all the features of a HP 16550A workbench logic analyzer. Check it out: My version of the fpga uses 85% of the slices, keeps the legacy triggers, meets timing easily (at 105Mhz), and adds: Trigger Terms: 10 more 32-bit masked value comparisons. […]