SUMP logic analyzer with 2 scope channels

hlipka made a logic analyzer with 2 oscilloscope channels that uses a Cypress PSoC chip. It works with SUMP clients like Open Logic Sniffer.  Goal of this project is to develop a combination of 2-channel oscilloscope with a 32-channel logic analyzer. Sample speed will be 1 Msps, with a depth of 6k samples (when using […]

All through-hole version of the Logic Shrimp

jarin made an all through-hole version of the Logic Shrimp logic analyzer: I’ve made variation of Logic Shrimp, using only through-hope components found in my junk box. More details and pictures can be found here. There is no schematics drawn, I built it just using datasheets and original schematics – and I’m too lazy to […]

OpenBench Logic Sniffer release 3.08

A new software package v3.08 is available for the Logic Sniffer: OpenBench Logic Sniffer Release 3.08 is now available for download. Release 3.08 includes Jawi’s 0.9.4 client with the following changes: Numerous Bug Fixes Support for multiple “Sump” clients Via the forum. Get a Logic Sniffer for $50, with free worldwide shipping.

Saleae Logic16 logic analyzer INSIDE and review

octal writes: Pretty impressive video review of Logic/ Logic16 (shows the insides as well) In this episode Shahriar takes a look inside the “Logic”, “Logic16″ and USBee SX which were reviewed in the previous episode. The PCBs get a closeup inspection along with some insight into the design of these products. Via the forum.

Windows-based Client (VC++, MFC)

flubberlab wrote a SUMP client that works with the Logic Sniffer: The client is pretty well tested (on WinXP Pro), but only offers a configuration and capture front end. Advanced triggers are not supported, RLE is unimplemented, and there is no waveform viewer. The captured data is exported to a VCD file for external viewing […]

Dangerous DSO part 4: Over simulated

Yesterday we covered the Dangerous DSO analog front end. This circuit divides our +/-10volt input to +/-0.5volts, and re-centers it between the 2volt and 3volt range the ADC can measure. Today we’ll simulate the circuit to get a better feel for how it works. Dangerous DSO is a new logic analyzer/oscilloscope design we’ve been using […]

Alternative Logic Sniffer client v0.9.4

Jawi just released version 0.9.4 of the forked SUMP logic analyzer client that works with the Logic Sniffer, Bus Pirate, IR Toy, etc. See topic starter post and/or the client’s home page for direct download URLs. The list of bugs solved in the final version is mostly the same to the latest RC. Major highlights […]

Logic Sniffer used in IDE bus sniffing and hard drive password recovery

Open Sesame on Prezi dop3j0e needed a way to recover the password on his ThinkPad’s hard drive after the laptop’s fingerprint scanner died (in which the password was stored.) Luckily, the drive’s IDE had 16 5V data lines just like the inputs on the OpenBench Logic Sniffer. He wired the Logic Sniffer to the lines […]

Logic Sniffer client v0.9.4 RC2

Jawi made another release candidate of the Logic Sniffer client : It is finally available: the second Release Candidate (RC) of the 0.9.4 version! Implemented features and issues solved in this release: VCD exports ignore selected channel groups Verify frequency measurement with RLE captures Support OLS-device profiles for BP, regular OLS and SUMP Add icon […]

New signal display component for Logic Sniffer client

Jawi released a preview of the new display component for the Logic Sniffer client: I’ve been working on an improved component for the display of captured signal data from the Logic Sniffer for some time now, and wanted to share the current results with you guys. Reasons for rewriting the component can be found on […]