Logic Sniffer advanced trigger support

flubberlab is diagramming the advanced triggers in the new Logic Sniffer Demon core in hopes of adding software support in the client. To understand the trigger system, and with an eye toward a trigger configuration user-interface (and application perhaps), I attempted to flesh-out the trigger resource and sequence illustrations shown in the OLS FPGA specification […]

All new Logic Sniffer FPGA core

dogsbody rewrote the entire Logic Sniffer FPGA core in Verilog and added nearly all the features of a HP 16550A workbench logic analyzer. Check it out: My version of the fpga uses 85% of the slices, keeps the legacy triggers, meets timing easily (at 105Mhz), and adds: Trigger Terms: 10 more 32-bit masked value comparisons. […]