Logic Sniffer: Updated VHDL code and continous sampling mode

While we all followed dogsbody’s work on the new Verilog Demon Core for the Logic Sniffer, kinsa cleaned up the old VHDL core:
  • New SPI code, works with the latest PIC firmware (v3.0)
  • Working Metadata command
  • New RLE code; n bit counters for n bit data width (except for 24 bits). Additional compression for cases with zero run lengths. RLE stop command is also implemented
  • Fixed the spurious triggers due to floating external trigger pin
  • Resolved timing issues
kinsa also wrote a new continous sampling mode bitstream that captures continuously at a blazing 10KHz:

On my netbook with version 3.0 of the PIC firmware, the system can only achieve a maximum sample rate of 10kHz for 8 bit samples. Currently, the bottleneck is the PIC USB transfer rate.

Included is a test SUMP client to demonstrate this new capability. Select Test Mode and memory depth of 256K. Test mode outputs the contents of a 32 bit counter incremented by the sample rate clock.

Note that triggering is ignored and RLE is not supported.

Amazing work, and all thanks to open source.

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