While we all followed dogsbody’s work on the new Verilog Demon Core for the Logic Sniffer, kinsa cleaned up the old VHDL core: New SPI code, works with the latest PIC firmware (v3.0) Working Metadata command New RLE code; n bit counters for n bit data width (except for 24 bits). Additional compression for cases […]
Tag Archives: RLE
Logic Sniffer RLE update
rasmus has another RLE update for the Logic Sniffer. The finish command is now 0x05. Timer removed in favor of the finish command. The code has been optimized and made easier to read. Two independent updates of the logic analyzer core are currently underway in the forum. There’s also updates to the Verilog version we […]
Logic Sniffer RLE update new version
There’s a new version of rasmus’ RLE update for the Logic Sniffer. This version has fixes for 8 and 16bit RLE, and new ways to dump RLE samples immediately. The finish now feature is probably something that the user wants. Responsiveness is good. You might think you want a 60 second timeout, but then you […]
Logic Sniffer RLE fix test
rasmus posted an updated Logic Sniffer bitstream with a bunch of fixes to RLE: 32-bit (31-channel) RLE works as before. 16-bit (15-channel) RLE works (I think) but the client doesn’t support it yet. You’ll see the raw RLE data in the client. 8-bit (7-channel) RLE works with the same caveats. All RLE modes time out […]