VHDL core – Dangerous Prototypes

Logic Sniffer: Updated VHDL core

kinsa posted an update of the VHDL core for the Logic Sniffer. Via the forum.

Logic Sniffer: Updated VHDL code and continous sampling mode

While we all followed dogsbody’s work on the new Verilog Demon Core for the Logic Sniffer, kinsa cleaned up the old VHDL core: New SPI code, works with the latest PIC firmware (v3.0) Working Metadata command New RLE code; n bit counters for n bit data width (except for 24 bits). Additional compression for cases […]