Logic Sniffer: Updated VHDL code and continous sampling mode

While we all followed dogsbody’s work on the new Verilog Demon Core for the Logic Sniffer, kinsa cleaned up the old VHDL core: New SPI code, works with the latest PIC firmware (v3.0) Working Metadata command New RLE code; n bit counters for n bit data width (except for 24 bits). Additional compression for cases […]

Logic Sniffer: Demon Core v3.07 and firmware updates

Dogsbody released Demon Core v3.07 for the Logic Sniffer with the following fixes: Fixes problem with demux DDR captures causing bogus glitches Fixes missed samples when armed. Ensures the finish-now command works cleanly Minor tweaks to the adv-trigger. A full spec Note: Please be sure to use Jawi’s 0.9.3 release (or newer)! We released an […]

Logic Sniffer: Demon Core v6

Dogsbody released v6 of the Verilog core for the Logic Sniffer, codename “Demon Core”. Try it with Jawi’s latest 0.9.3.1 client software: Feb 8 Edit: Release6. Removed inclusive-RLE mode, since breaks older clients and is no longer used by Jawi’s. Also fixed 24-bit RLE counts. Note: Please be sure to use Jawi’s 0.9.3 release (or […]