We spotted an Open Logic Sniffer in Adafruit’s weekly Ask an Engineer Chat. It looks like they’re soldering it up on a reflow plate. We like the warning that the reflow plate may be a hot surface.
Category Archives: logic analyzer
Open Logic Sniffer demo and testing videos
Jack has a bunch of Open Logic Sniffer tutorial and testing videos at the Gadget Factory. There’s also a demo on YouTube, and a high quality screencast. The Open Logic Sniffer is currently available for preorder at Seeed Studio for $45, including worldwide shipping.
Logic analyzer name
We’ve been working on an open source logic analyzer with Jack Gassett of the Gadget Factory. The project was known by the code name ‘SUMP-PUMP’, but you helped suggest a name. There were lots of great suggestions in the comments and the forum. Thank you. LukeS suggested the name Logic Sniffer. He’ll get one of […]
Prototype: Openbench Logic Sniffer logic analyzer
The most recent documentation is now on the wiki Openbench Logic Sniffer is an open source logic analyzer. It’s designed to support the SUMP logic analyzer software at the lowest possible cost. Download the source and design files from the Gadget Factory project page. This project started in the comments on a post. Initial circuit […]
SUMP PUMP challenge completed
We’ve been working on an open source logic analyzer prototype with Jack Gassett of the Gadget Factory. The project is currently known by the code name ‘SUMP-PUMP’, but you can help suggest a name. The design incorporates elements of the Butterfly platform, which is available now at the Gadget Factory. On Wednesday we offered a […]
Write an app, get a SUMP PUMP
We’ve been working on an open source logic analyzer prototype with Jack Gassett of the Gadget Factory. The project is currently known by the code name ‘SUMP-PUMP’, but you can help suggest a name. The design incorporates elements of the Butterfly platform, which is available now at the Gadget Factory. Update: Michal Demin completed this […]
SUMP PUMP testing
We’ve been working on an open source logic analyzer prototype with Jack Gassett of the Gadget Factory. The project is currently known by the code name ‘SUMP-PUMP’, but you can help suggest a name. The design incorporates elements of the Butterfly platform, which is available now at the Gadget Factory. Jack finished a bunch of […]
Logic analyzer firmware development update
Today we completed an initial PIC firmware for the open source logic analyzer. The PIC has two operating modes: a serial bridge for SUMP to talk to the client on the FPGA, and a ROM programmer that updates the AT45DB041D flash chip with new logic for the FPGA. There’s still some bugs, but the design […]
Open source digital sampling oscilloscope
Please join us in the forum to discuss a digital sampling oscilloscope add-on for the open source logic analyzer (currently referred to as project SUMP PUMP). Our general goal is to design an inexpensive expansion board that samples analog voltages at 50MHz+. The combination of a logic analyzer and sampling oscilloscope is a powerful debugging […]
Name the open source logic analyzer, get one free
We’ve been working on an open source logic analyzer prototype with Jack Gassett of the Gadget Factory. Gerbers will go to the board house before the end of this week. Until now we’ve called this project by the codename ‘SUMP PUMP’, because it’s a data pump for the open source SUMP logic analyzer client. This […]
Open source logic analyzer update
A few months ago we started working with the Gadget Factory to build an open source logic analyzer. After a very successful collaboration, we’re almost ready to order the first PCBs. Click here for a large PCB image [PNG]. The draft device has 16 buffered (5volt tolerant) input channels, and 16 unbuffered I/O channels on […]
Arduino logic analyzer
Merve is working on an Arduino-driven logic analyzer design in the Arduino Forum. It uses logic chips to drive SRAM memory during acquisition, the Arduino then dumps samples from the SRAM via a shift register. We’re really interested in the result of this design. We once attempted a logic chip-based analyzer, but the design got […]
Open source logic analyzer update
Development of the open source logic analyzer, first discussed here, has progressed rapidly in the forum. We’ve looked at cost estimates, Uwe made some excellent block diagrams, and Jack has already added a basic layout to his SVN. Read our goals and specs after the break.
Open source logic analyzer development
We’re really excited to be joined by Jack Gassett, developer of the Butterfly FPGA platform, to prototype an open source, high-speed, low-cost logic analyzer. This effort grew out of a bunch of great comments on a post about open source logic analyzer clients. Share your ideas for the logic analyzer in the new ‘SUMP PUMP’ […]
Bus Pirate logic analyzer mode
See the latest version on the documentation wiki. This is an updated guide to the Bus Pirate logic analyzer mode, it expands on the initial documentation posted earlier. Bus Pirate firmware v3.0 introduced a logic analyzer mode that works with the SUMP open source logic analyzer client. The logic analyzer can record 4096 samples at […]
HVR-1600 Performance and Reverse Engineering
Check out this epic battle between man and I2C EEPROM. Devin wanted to fix a bug in the Linux driver for his HVR-1600 TV tuner card. He suspected that the Linux driver didn’t configure the board correctly, so he sniffed the I2C-based configuration traffic under Windows with a Saleae Logic. There’s a great overview of […]
Open source logic analyzer clients
Today we played with a few open source logic analyzer clients in preparation for an upcoming prototype. The best we found is SUMP, written in Java. There’s also compatible host software for several FPGA development boards, we found even more ports floating around the web. SUMP has a SourceForge page, but it doesn’t look very […]