Building a CPLD based logic analyzer


Alex from InsideGadgets has been working on a Building a CPLD Based Logic Analyser. In Part I of his post he details his build of a logic analyzer which saves the sample to external SRAM.

For this project Alex used the Altera MAXII EPM240 development board with an on board 20MHz oscillator. The coding was done in Verilog. Details including the code and schematic can be found on InsideGadgets.

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