Categories

Building a CPLD based logic analyzer

Posted on Tuesday, January 21st, 2014 in builds, code, CPLD, how-to, logic analyzer by the machinegeek


Alex from InsideGadgets has been working on a Building a CPLD Based Logic Analyser. In Part I of his post he details his build of a logic analyzer which saves the sample to external SRAM.

For this project Alex used the Altera MAXII EPM240 development board with an on board 20MHz oscillator. The coding was done in Verilog. Details including the code and schematic can be found on InsideGadgets.

This entry was posted on Tuesday, January 21st, 2014 at 6:00 pm and is filed under builds, code, CPLD, how-to, logic analyzer. You can follow any responses to this entry through the RSS 2.0 feed. You can skip to the end and leave a response. Pinging is currently not allowed.

Leave a Reply

Notify me of followup comments via e-mail. You can also subscribe without commenting.

Recent Comments

  • Joe Desbonnet: Ya, I can recommend the low melting point solder. I used brand 'ChipQuik' and it's amazingly easy to use.
  • Jerome: I need a new BusPirate for the Fablab ;) Many thanks!
  • Max: Seems like an unexpectedly violent way to remove the chip indeed. A hot air station should of course do the job just fine, but in...
  • jose: Part removal described here is pure butchery, the cheapest hot air station will do a fast and clean job removing the QFP, heat air to...
  • Cody: Yes please