PLUNIFY: programmable logic design simplified

Posted on Saturday, January 15th, 2011 in CPLD, FPGA, site by the machinegeek

A new site allows you to conduct programmable logic design with Xilinx and Altera devices “in the cloud.” PLUNIFY, currently in Beta, allows you to experiment with PLD development in your web browser without downloading any software. A free account is available allowing you to 1 GB of storage space and free online development tools to create and simulate designs in Verilog and VHDL. Other features are available on a subscription basis such as online implementation and device matching.

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3 Responses to “PLUNIFY: programmable logic design simplified”

  1. Drone says:

    For free you don’t get 1GB you get half that and you are forced to run at 0.5X speed on a shared server constrained to “common devices”. This site is a front-end for open source simulators; Icarus Verilog and GHDL for VHDL.

    The complete terms and conditions are rather difficult to interpret IMHO. For example…

    The FAQ says:

    Currently our services are free for a limited period. Simulation features will always be available at no cost. For the design compilation / implementation, benchmarking and verification services, subscription plans tailored to specific needs are available.

    But under Price Plan it says:

    Multiple Tool Versions
    1 GB Storage
    50 Hours
    Multiple Devices

    (So what’s this “50 Hours” limitation?)

    Then when you go to sign-up for the free account it says:

    USD $0
    Shared Server
    0.5X Speed
    500MB Storage
    Common Devices

    My conclusion: I consider time to be valuable. I would be hesitant to invest my time learning a new system without full disclosure of the costs should I decide to continue. The value-added services are interesting though. If you have “free” time, I guess there’s no harm done playing with this :-)

  2. Harnhua says:

    Thank you for your comments.

    Sorry about the 1 GB typo for the free account’s storage quota–it should be 500 MB.

    The “50 hours” refers to the amount of server CPU-hours that you get in the Starter plan for compiling your designs. Users’ time is very important and one of the things we hope to do is to exactly to reduce the amount of time involved in the development process.

    Simulation services using Icarus Verilog and GHDL are free but are limited to the free servers. We are not charging for services yet and are working out the details of how to provide a sustainable service (someone’s gotta keep those servers running ; ) ) that serves the community’s needs.

    Currently we are still in beta and would love to hear feedback like yours, your feature requests, what you like and don’t like about our site.


  3. Evgeni says:

    This is a move in the right direction.
    The main advantage of this tool is convenience: no need to install anything. However, it can become quite expensive to build large and high-speed FPGA designs. Such builds can easily take several hours, or even a day.

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