Bus Pirate “Ultra” HDL moves from simulation to real hardware

The HDL is complete enough to start testing on real hardware. This update puts almost every feature under control of the state machine in the FPGA so commands can be pipelined with repeatable precision. Commands (write/read SPI, set/clear pin, measure voltage, update PWM, enable pull-up resistors, etc) are pushed into a FIFO buffer using a […]