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Understanding Verilog warnings

Posted on Friday, September 23rd, 2011 in documentation by Ian

Big Mess o’ Wires has a review of Verilog warnings:

Those of you who’ve followed the blog for a while know about my many frustrations with Verilog. Because it feels sort of a like a procedural programming language, but very definitely isn’t one, I keep expecting to be far more competent at Verilog design than I actually am. While working on Plus Too, the Xilinx synthesis tool reported many, many warnings that I didn’t understand. The warning list grew to at least 100, and was so long that I just stopped reading it. That was dangerous, as most of the warnings were likely problems that needed to be addressed.

This entry was posted on Friday, September 23rd, 2011 at 6:45 am and is filed under documentation. You can follow any responses to this entry through the RSS 2.0 feed. You can skip to the end and leave a response. Pinging is currently not allowed.

One Response to “Understanding Verilog warnings”

  1. Drone says:

    Go here:

    http://www.sutherland-hdl.com/papers.php

    Look under 2006 and 2007 for the two Verilog Standard Gotchas papers and presentations by Stuart Sutherland. Enjoy…

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