Dangerous DSO part 4: Over simulated

Posted on Thursday, May 12th, 2011 in FPGA, logic analyzer, oscilloscope, Prototypes by Ian

Yesterday we covered the Dangerous DSO analog front end. This circuit divides our +/-10volt input to +/-0.5volts, and re-centers it between the 2volt and 3volt range the ADC can measure. Today we’ll simulate the circuit to get a better feel for how it works.

Dangerous DSO is a new logic analyzer/oscilloscope design we’ve been using in the lab. This is not a finished project, it will not be produced. We’re posting our current progress to get some feedback. Look for a new Dangerous DSO article every day this week. Don’t miss Part 1: There’s so much between 0 and 1, Part 2: Feed and water your ADC, and Part 3: Messing with the front end.


We used the free LTspice circuit simulation software, our simulations are available in the latest downloads.

LTspice has a crappy schematic editor, second only to the Xilinx Webpack schematic entry program in suckage. Seriously.  We managed to enter our front-end design with the default values from the Bitscope schematic.


Remember this diagram. We want to divide the +/-10volt input down to +/-0.5volts, then offset it 2volts.

Right click->run to simulate the design. A pretty graph appears that shows the voltage at various points in the circuit as the DSO input goes from -10volts to +10volts.

Input (green) goes from -10v to +10v. This is a simulation of voltage coming into the scope probe.

After the voltage divider (red) the signal is reduced to -0.5v at -10volts input and +0.5v at +10volts input. Perfect.

Output voltage (blue) shows what the ADC gets from the op-amp. 2v at -10volts, to 3.7v at +10volts. No good! We need to be centered in the 2volt-3volt measurement range of the ADC.

Fixing the gain

What’s going on? Gain. Remember from yesterday that the Bitscope ADC buffer stage multiplies the input by 1.667. Gain is determined by R1 and R2 in the simulated circuit.

  • Vout=(1+R2/R1)*Vin.
  • To solve for gain set Vin=1 and enter the resistor values
  • Gain=(1+(220/330))=1.667

This is exactly what we got, ~1.7Vp-p from our 1Vp-p signal.

We can compensate for the gain by adjusting the input voltage divider. We can also reduce the gain by changing the value of R1 and R2, but we can’t reduce it to 1 in the current circuit.

After a lot of experimenting we decided to increase the gain to 2x by setting R1 and R2 to the same value (220 ohms). The zero adjustment got really close to the edge of the pot with any 1.667 gain setup, 2x gain leaves lots of room to play.

A gain of 2 means we have to divide the input by an additional factor of 2. The 20Vp-p input is now divided to +/-0.25volts (0.5Vp-p). The op-amp then amplifies the signal by a factor of two and offsets it to the ADC measurement range. It probably does awful things to the signal, but we don’t care at this point.

  • 0.975M+0.025M=/40=+/- 10volt input
  • 0.950M+0.050M=/20=+/- 5volt input
  • 0.900M+0.100M=/10=+/- 2.5volt input

For +/-10volt input we’re now using a .975M and .025M resistor divider. Most of the useful divider values are in the bottom 100K of the 1M resistor. It would be a lot easier to control the input range with a 900K fixed resistor and 100K trimmer.

Simulate the new values

This is a simulation of the front-end with the new values.

Input from the DSO probe (green) goes from -10v to +10v. Offset voltage (light blue) measured at R1 is constant at around 2.5v.

After the voltage divider (red) the signal is reduced to -0.25v at -10volts input and +0.25v at +10volts input. Perfect.

Output voltage (blue) from the op-amp is 2v at -10volts, to 3v at +10volts.  Perfectly centered in the 2volt-3volt measurement range of the ADC.

Looks great, this will be the basis for tomorrow’s test.

Other circuits

There’s lots of other ways to handle the voltage offset. A second slow op-amp pair can first buffer, then invert, the 2.5volt common mode voltage from the ADC. That’s something to try on a future revision.

Still to come

Tomorrow concludes a week of Dangerous DSO. We’ll test the board with the updated gain values and a modified range divider.

Don’t miss

This entry was posted on Thursday, May 12th, 2011 at 5:40 am and is filed under FPGA, logic analyzer, oscilloscope, Prototypes. You can follow any responses to this entry through the RSS 2.0 feed. You can skip to the end and leave a response. Pinging is currently not allowed.

7 Responses to “Dangerous DSO part 4: Over simulated”

  1. Schazamp says:

    I’ve really enjoyed this series, keep up the good work!

  2. JanW says:

    The 0.975 M resistor and the opamps parasitic input capacitance form a first order lowpass with a -3 db point at approx. 6.5 MHz. You’re sacrificing bandwidth.

    • Ian says:

      Any advise on how to handle that? The Bitscope uses some BJTs on the inputs and has a much fancier range selection front-end, but I was just going for the simplest thing possible.

      • JanW says:

        Add a compensation capacitor in parallel to the 975k resistor. I can’t give an exact value because it depends on other parasitics as well.


  3. MarkK says:

    Adding just a compensation capacitor in the input signal path will not be sufficient — in addition to the signal path rolloff, the parasitic input capacitance of the noninverting input will cause the AC gain of your amplifier to increase as frequency goes up. Since you have rolloff @ one frequency going on in the input side and peaking at a different frequency on the feedback side, the best approach is to put two variable capacitors in your circuit — one across your 970K resistor and one across your 220 ohm resistor. The capacitor ratios need to be the same as the resistor ratios. To calibrate, you would connect a square wave directly to the amplifier’s noninverting input and adjust the feedback capacitor to get a square wave, then feed a square wave into your input signal path and adjust that capacitor.

    Adding more gain stages or fancier input attenuation networks makes things even more complicated. Some of the reasons that high performance ‘scopes are expensive.


    • PapaD says:

      I agree with Mark, but an emitter follower input stage (as explained in my post to part 3) would very much lower the potential divider impedance putting the 3dB point outside of the bandwidth of the ADC. I would go with the emitter follower as the first stage to give me the required attenuation & bias point followed by a common-emitter amplifier.

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