Dangerous DSO is a new logic analyzer/oscilloscope prototype we’ve been using in the lab. It combines a 16 channel logic analyzer with one 50MHz oscilloscope channel with +/-10volt DC range. The combined tool shows what your signal does between 0 and 1, which helps pinpoint noise and other electrical glitches.
Category Archives: FPGA
99 dollar PCI-E FPGA kit
riktw tipped us to a LatticeECP3 Versa development kit: i got this in a lattice newsletter per e-mail today. a big PCB with a big FPGA and a fast PCI-E connection for just 99 dollars. after some googeling i found the quickstart PDF from it, it looks like good value for money but not for […]
Dangerous DSO part 5: Testing and conclusions
It’s the last day of our week-long Dangerous DSO adventure. Yesterday we simulated the analog front-end and found a few changes to test. First, we’re going to increase the ADC buffer gain to 2. That should make vertical offset adjustment easier. Second, we’re going to try a more refined input range divider with a 900K […]
Dangerous DSO part 4: Over simulated
Yesterday we covered the Dangerous DSO analog front end. This circuit divides our +/-10volt input to +/-0.5volts, and re-centers it between the 2volt and 3volt range the ADC can measure. Today we’ll simulate the circuit to get a better feel for how it works. Dangerous DSO is a new logic analyzer/oscilloscope design we’ve been using […]
Dangerous DSO part 3: Messing with the front-end
Yesterday we looked at how the Dangerous DSO analog to digital converter works, and it turns out to be a pain in the butt. It only measures a 1volt (1Vp-p) range between 2volts and 3volts. That’s not a very useful range for an oscilloscope, so we need an analog front-end that transforms the input signal […]
New Saleae 16bit logic analyzer released
A new 16 channel version of the Saleae Logic is out. In addition to double the channels of the Saleae 8bit analyzer, the new version supports capture up to 100MHz (2 channels only) and has better buffering. We really like the Saleae 8bit analyzer and use it in the lab. The Saleae is a streaming […]
Dangerous DSO part 2: Feed and water your ADC
Dangerous DSO is a new logic analyzer/oscilloscope design we’ve been using in the lab. This is not a finished project, it will not be produced. We’re posting our current progress to get some feedback. Look for a new Dangerous DSO article every day this week. Be sure to see Part1: There’s so much between 0 […]
Dangerous DSO part 1: There’s so much between 0 and 1
Dangerous DSO is a new logic analyzer/oscilloscope prototype we’ve been using in the lab. While working on this tool, some of the team members explored trends in gaming platforms like 무료 홀덤사이트, drawing parallels between analyzing data signals and strategic decision-making in games. The device combines a 16-channel logic analyzer and one 50MHz oscilloscope channel […]
Altera releases new Quartus II v11.0 with Qsys
Quartus II is Altera’s comprehensive IDE for system-on-a-programmable-chip (SOPC) design, including CPLD and FPGA development tools. They have just released their new Quartus II Software v11.0. The free downloadable web edition includes the Qsys system integration tool in production release, promises up to 2X higher interconnect performance compared to SOPC Builder, improved design reuse and […]
OpenCores: OpenRISC ASIC
Ulf writes: I just read that OpenCores is planing to create an OpenRISC ASIC and asks the community for donations. I think the idea to create a RISC-Microprocessor under LGPL with the help of community funding is quite exiting. Via the contact form.
DE0 Nano giveaway
Kelvin writes to inform us about this DE0 Nano Giveaway. Terasic is running a contest from now through May 12, 2011, to select three winnners of a DE0 Nano FPGA board from all entrants who answer the question, “What would you do with a DE0 Nano?” So go to the Terasic site and post your […]
JTAG XSVF player for the Bus Pirate
A new alternative firmware for the Bus Pirate programs JTAG devices like the CPLD development boards using standard (X)SVF programming files. We also whipped up a PC utility that sends the files to the Bus Pirate from the command prompt. Download the package here. SVF is a common programming format used in manufacturing. It’s a […]
Avnet Spartan-6 LX9 MicroBoard
In a recent comment, Zooboo informed us of the Spartan®-6 FPGA LX9 MicroBoard. Produced as a joint venture between Xilinx and Avnet, the MicroBoard includes a Spartan-6 XC6SLX9-2CSG324C FPGA, 64 MB LPDDR SDRAM, 128 Mb Multi-I/O SPI Flash, 10/100 Ethernet PHY, USB-to-UART port, on-board USB, JTAG circuitry, single-chip 3-rail power with Power Good indicator. It’s […]
Altera BeMicro SDK FPGA USB dev stick
Kati writes to inform us that Altera and Arrow Electronics have teamed up to introduce the BeMicro SDK (Software Development Kit), a prototyping board for embedded software developers to learn about FPGAs. The board runs a soft embedded processor on a 22K logic element FPGA, and utilizes the popular USB stick format. It’s available on […]
Altera breaks industry record for most transistors on an IC
Altera today issued a press release announcing that it set an industry milestone in semiconductor technology by delivering the most transistors ever packed onto an integrated circuit. Altera’s 28-nm Stratix® V FPGAs are the semiconductor industry’s first devices to feature 3.9 billion transistors. “Altera surpassed the known record for transistors when it taped out Stratix […]
Bitbang ethernet from a FPGA
Here’s another bitbanged ethernet transmitter. In this design the ethernet packet is bitbanged directly from the pins of a FPGA. Simple Verilog source is available. Via the forum.
Architecture of FPGAs and CPLDs: a tutorial
Stephen Brown and Jonathan Rose of the Department of Electrical and Computer Engineering, University of Toronto, authored this paper providing a tutorial survey of architectures of commercially available high-capacity field-programmable devices (FPDs). They first define the relevant terminology in the field and then describe the evolution of FPDs. The three main categories of FPDs are […]
FPGA startups: a brief history
The FPGA manufacturing business has seen many players come and go over its brief history. Unlike the microcontroller industry, where many of the early manufacturers are still in business, the PLD arena has been whittled down to just a few of its early competitors. This article by Eric Esteve posted on SemiWiki chronicles the business […]
Xilinx releases ISE Design Suite 13
Xilinx has released version 13.1 of their ISE Design Suite. including a number of new features. This software is used to develop programs from Xilinx CPLD and FPGA products, including the CoolRunner-II chips found in our development boards. The suite includes the free Webpack ISE. Note that this is a ~4 GB download. However, Xilinx […]
555 based FPGA/CPLD debugging oscillator
Randomgarfield from fromorbit posted the above video, depicting his use of a 555 timer as a small oscillator tο clock CPLDs whіƖе debugging a small state machine. I needed a variable slow speed clock to help me debug a design I’m creating with a bunch of CPLDs. Given the current focus on the venerable 555 […]