The FPGA manufacturing business has seen many players come and go over its brief history. Unlike the microcontroller industry, where many of the early manufacturers are still in business, the PLD arena has been whittled down to just a few of its early competitors. This article by Eric Esteve posted on SemiWiki chronicles the business cycle of various FPGA manufacturers and analyzes their successes and failures.
“Atmel not doing so well?” They are currently profitable… With a PE of about 15 that seems pretty normally healthy to me they were operating at a loss but their MaxTouch line is getting them lot of design wins and profits…
Yes, Atmel is Not doing well in FPGAs, that is what the article is about FPGAs, not semiconductor companies. Atmel is doing fine everywhere else except FPGAs in which they haven’t done anything in at least the past 5 years. With the AVR/Arduino popularity it could be a perfect time for them to respin the FPSLIC product line (AVR+FPGA) it would certainly do well in the hobbyist market not huge volumes but with so many people using the AVRs it could see a ground swell and eventually built to a sucess. Xilinx & Altera make good products but don’t seem interested in smaller projects they want to concentrate on selling their large chips in dense BGA packages which strongly limits prototyping. Something like the FPSLIC could easily take over the low end (higher volume).
The Tabula FPGA design mentioned in the article is actually pretty clever despite sounding a little hokey at first. By grouping several (eight in their case) LUTs/register elements together and allowing the system to select a different logic element on each clock cycle, you can make the FPGA look larger. Obviously you still need more silicon for a bank of logic elements vs. a single logic element, but the big area hog in large FPGAs is usually the interconnect mesh.
For designs that aren’t highly parallel (where many/most of the logic elements are used on every clock), you’d see the same number of logic elements as on a larger FPGA, but your interconnect mesh would be much smaller. Having a smaller mesh and being able to recycle unused interconnects on different time slices also allows you to reduce your average connection length, which should speed up your design.
It would be interesting to experiment with fitting different designs on a Tabula FPGA vs. a Xilinx or Altera FPGA.
microsemi/atmel’s smartfusion fpga line is really interesting… lots of digital cells of course, but also programmable analog blocks (adc, dacs etc) too! Built in flash so no external configuration device needed, and a hard arm ip for a full soc design. I bought their $100 eval board and it works nicely… although coming from altera I found their libero software to be a little clunkier.
Unfortunately, it has an uphill battle against altera/xilinx, so I just hope its able to survive!