555 based FPGA/CPLD debugging oscillator

Randomgarfield from fromorbit posted the above video, depicting his use of a 555 timer as a small oscillator tο clock CPLDs whіƖе debugging a small state machine.

I needed a variable slow speed clock to help me debug a design I’m creating with a bunch of CPLDs. Given the current focus on the venerable 555 timer IC, I thought rather than using my usual AVR/PIC solution I’d create something with the handy little timer.

I wanted a guaranteed 50% duty cycle, so I paired the 555 with a 74HC74 flip-flop in a clock divider set up. The flip-flop divides the 555’s frequency by half giving you a perfect 50% duty cycle no matter what the 555’s duty is.

The 555 generates a clock in the range of 0.4-1.2KHz, but after the division the board outputs about 0.2-660Hz from the flip-flop, perfect for my requirements.

Since I only had SOIC NE555D in my parts bins and I only had DIP 74HC74’s I’ve ended up with an mix of SMD and through-hole technologies. The DIP has two flip-flop, but I’ve wired them in parallel so that one drives the output and an open-collector transistor (handy for 3.3v circuits) and the other drives a LED built into the cases power-switch.

The box has an internal 9V battery or can have it’s power supplied by the circuit (5V, 3.3V circuits will use the battery).

While no schematic is furnished, the construction should be straightforward. The rate of the 555 appears to be varied using a potentiometer.

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