Dangerous DSO is a new logic analyzer/oscilloscope design we’ve been using in the lab. This is not a finished project, it will not be produced. We’re posting our current progress to get some feedback. Look for a new Dangerous DSO article every day this week. Be sure to see Part1: There’s so much between 0 and 1.
Analog to digital converters are common on small microcontrollers, they’re handy for measuring voltage from a sensor. Top speeds are usually less than 1 million samples per second.
The Dangerous DSO oscilloscope also uses an ADC to measure voltage, but it’s much faster. We’d like our ADC to work at the 100-200MSPS maximum rate of the logic analyzer part, but a professional DSO would be even faster.
At high-speeds things start to get complex. High-speed ADCs have a very narrow input range and other specific requirements. Today we’ll look at the Dangerous DSO analog to digital converter. Tomorrow we cover our attempt to satiate the beast with an analog front-end.
To get respectable speed from a DSO we need an analog to digital converter with a parallel interface. The ADC measures voltage and puts the reading on 8 output pins. Fresh measurements pop out the ADC_Dx pins every time the clock pin (ADC_CLK) goes high to low.
Dangerous DSO uses a TI ADS830 analog to digital converter with a maximum speed of 60MHz. We run it at 50MHz for testing. The ADS830 is low cost, compared to some, but not exactly cheap.
Logic analyzer channel 3 is connected to the ADC output pins. During capture the FPGA stores the ADC output just like the logic analyzer channels. The SUMP clients already have a scope mode that displays the channel as an analog graph.
ADC input range pains
We’re spoiled by microcontroller ADCs. They’ll usually measure a voltage between ground and the supply. If your system is 5volts, the ADC will measure from 0volts to 5volts. An 8bit ADC reading of 254 (254/255*5volts) represents ~4.9volts, somewhere near the top of the range.
High-speed ADCs have a very limited measurement range, usually only 1 or 2volts. This is a pain, but easy enough to solve with a resistor divider. The swing is noted as Vp-p in datasheets, the voltage difference between the highest and lowest points of the signal.
The real bummer comes from the center or common mode voltage. Input can only swing one volt, and it has to be centered at 2.5volts. That means the lowest we can measure is 2volts, and the highest is 3volts. We can adjust the top and bottom references, but our ADC is optimized to work best in this range.
2volts to 3volts isn’t a very useful measurement range for an oscilloscope. We need an analog front-end that divides the input voltage into the 1Vp-p range the ADC will accept, and then centers it at 2.5volts. This is where black art DSO design happens. It’s a safe bet that our design is a dud.
For a 0-10volt DC input range we would need to:
Depending on the input range there are a lot of different ways to do this. We’ll explain our sucky front-end design and simulate the circuit later this week. Warning, there be op-amps in these woods.
Analog parts of the ADS830 run at 5volts, the digital pins run from a separate 3.3volt supply. There’s lots of juicy decoupling capacitors for the various supply pins and references. Not all of them are actually needed, and a few cause problems like the extra 10uF on the CM pin.
Internal references are enabled by grounding the !INT/EXT pin. Each reference (REFT and REFB) pin gets a 2.2uF and 0.1uF decoupling capacitor. REFT is the top or high level reference for the ADC, the internal reference is 3.0volts. REFB is the bottom or low level reference, the internal reference is 2.0volts.
An internal connection between the top and bottom reference create a center reference on the CM pin. The 2volt and 3volt internal references have a 2.5volt center reference.
The ADC has differential inputs that we don’t need, so we tied the inverting input to the 2.5volt center reference. Now the non-inverting input can be used like a normal single-ended ADC.
RSEL selects a 1Vp-p or 2Vp-p measurement range. Technically the ADS830 can measure 1.5volts to 3.5volts, but we don’t think the internal reference configuration supports that. Rather, now we don’t think that. Earlier we did, and we designed the analog front-end around a 2Vp-p range. More about that bug later.
Internally RSEL is pulled-up to 5volts, which would damage the 3.3volt FPGA pins. A small transistor circuit (cut off in the image above) grounds RSEL to enable 1Vp-p operation. This is can probably be tied to ground permanently instead.
The ADS831 is an 80MHz ADC with the same pinout, but it requires a 5volt clock signal. It won’t work with the FPGAs 3.3volt output. Even if a faster ADC is used it wouldn’t necessarily mean more speed. We haven’t figured out how to use the full 60MHz of the current ADC, it’s just tied to the inverse of the 50MHz system clock. A true 60/80/100MHz ADC sample rate will require some additional clock trickery.
Still to come
All week we’ll post details about the analog design: