Dangerous DSO part 3: Messing with the front-end

Posted on Wednesday, May 11th, 2011 in Development, FPGA, oscilloscope, Prototypes by Ian

Yesterday we looked at how the Dangerous DSO analog to digital converter works, and it turns out to be a pain in the butt. It only measures a 1volt (1Vp-p) range between 2volts and 3volts. That’s not a very useful range for an oscilloscope, so we need an analog front-end that transforms the input signal into something the ADC will measure.

Lets set a +/-10volts DC input range goal for our feeble first attempt at a DSO. That’s a 20volt swing from top to bottom(Vp-p). Input to the DSO will be divided by 20 so it has a 1Vp-p range. Then we need to lift it 2 volts into the 2-3volt measurement range of the ADC. Some gory details below.

Dangerous DSO is a new logic analyzer/oscilloscope design we’ve been using in the lab. This is not a finished project, it will not be produced. We’re posting our current progress to get some feedback. Look for a new Dangerous DSO article every day this week. Don’t miss Part 1: There’s so much between 0 and 1, and Part 2: Feed and water your ADC.

Front-end circuit

The Bitscope logic analyzer/oscilloscope was originally an all through-hole project in Circuit Cellar magazine. A CPLD drives two 32Kx8 SRAM chips that store 8 channels of logic and 8bits from a flash ADC chip. Sound familiar? Top capture speed is 50million samples per second.

Fascination with the Bitscope is the reason Dangerous Prototypes exists today. Our first open source logic analyzers cloned the Bitscope protocol instead of SUMP. We’ve been building bits and pieces of it for years. In short, a Bitscope clone has been a long term goal. But enough gushing, more thieving.

We dug through the Bitscope design to see how they handled the ADC input. Just the minimum circuit to get a ground-centered voltage into the ADC. The Bitscope ADC buffer is exactly what we need. An op-amp lifts a 1.2Vp-p signal to a range the ADC can use. It’s adjustable and works with different ADCs, including a few with the same specs as the ADS830 we’re using. It has 1.667 gain by default, but we can deal with that later.

Voltage divider

To get 1Vp-p from +/-10volt input, a swing of 20Vp-p, we need to divide the input by 20. We used a 1Mohm trimmer resistor (R12) so we can adjust the input range. 1Mohm places a very small load on the circuit it connects to, but shouldn’t change the signal too much. Instrumentation quality isn’t a goal, we’re just prototyping.

We used a standard probe connector, but a banana plug might be better. Who has o-scope probe cables? Everyone has a multimeter cable, and it’s cheaper. C44 and C33 are for filter caps, if we ever get around to trying them.

Now we’ve got a +/- 10 volt signal divided down to +/-0.5volts. We still need to move it up to the 2-3volt range the ADC measures. Next up, a trip to the op-amp.


There’s no easy way around it, this project needs an op-amp. It’s gonna be confusing, and probably expensive. Our understanding might even be wrong, don’t use this to study for an exam.

An op-amp does two things we so desperately need. It can recenter the input signal from ground to 2.5volts. After the 1Mohm divider the signal is pretty weak, the op-amp adds some kick so it has enough power to drive the ADC.

We used the Bitscope ADC buffer verbatim, but removed the over-voltage protection diodes. The op-amp needs a +/-5volt supply. The negative voltage comes from a TCM828 inverter that just needs a few capacitors. USB isn’t always 5volts, it’s probably best to use the external power supply if a clean 5volt reference matters.

Input from voltage divider (R12) drives the op-amp’s non-inverting input (+).  The inverting input (-) connects to an adjustable negative voltage created by R8 and T1. C3,4,5,20 are filters.

An op-amp lives to keep the the voltage on both input pins equal, it tries to do this by changing the output voltage.  If the input on the + pin goes up 0.1volts, the op-amp increases the output voltage until the other input (-) goes up 0.1volts too.

R33 and R44 are key. They form a voltage divider between the op-amp output and the – input. We can manipulate this divider to change the output. If the voltage on the – input is half the output, then the output has to increase twice as much to equalize the + and – pins when + changes.  0.1volts increase on the + pin causes a 0.2volts increase in output to compensate on the – pin. This is gain. Or at least how we understand it. The Bitscope circuit has 1.667 gain, but we’ll play with that more tomorrow in simulations.

Back to the task at hand, shifting our ground to 2.5volt for the ADC.  The adjustable negative supply connected to the inverting input forces the op-amp to shift the output to compensate.  The center point can be set by changing the negative supply with R8. We used a single turn pot and it doesn’t give nearly enough room for fine adjustment.

Choosing an op-amp

Not just any op-amp will do, it has to be high speed and low distortion. You might notice some flywire rework on the op-amp. We’re testing lots of op-amps and they aren’t all pin-compatible.

The MAX477 used in the Bitscope design is discontinued. We looked for op-amps in current production with similar values: 300MHz -3dB bandwidth (at 1Vp-p if specified) and 1100V/µs slew rate. There are other factors to consider, but this helps narrow down the candidates.

MAX4450 is a recommended replacement, but the specs aren’t as nice (210MHz -3dB bandwidth, 485V/µs slew rate). An SOT-23 version is available at Digikey for $1.20, but we sampled the SOIC version for prototyping.

OPA2830 is our current favorite (230MHz -3dB bandwidth, 500V/µs slew rate), available from Mouser for $2.40. We’ll post results of future tests.

Summing it up

Now we have an analog front-end. A trimmer resistor divides the input signal down to 1Vp-p. The op-amp re-centers the signal at 2.5volts so we can measure it with the ADC. Both input range and the ground center can be adjusted.

Still to come

Next time we’ll simulate the design in LT-SPICE. It makes a lot more sense when you see it happen on a pretty graph.

Don’t miss

This entry was posted on Wednesday, May 11th, 2011 at 11:46 am and is filed under Development, FPGA, oscilloscope, Prototypes. You can follow any responses to this entry through the RSS 2.0 feed. You can skip to the end and leave a response. Pinging is currently not allowed.

22 Responses to “Dangerous DSO part 3: Messing with the front-end”

  1. Markus Gritsch says:

    Can you describe the purpose of T1? Why not simply connect R34 to GND? The pot could be inserted between R33 and R34 to make the negative input voltage adjustable.

    • Markus Gritsch says:

      Edit: I meant “connect R34 to -5V”

      • SQKYbeaver says:

        the purpose of the transistor is a more stable voltage reference.

        a negative voltage reference ic could be used instead but this allows it to be adjusted. i have a feeling there should be a zeiner in there too.

    • Ian says:

      The honest answer is I don’t know. Someone more experienced used it successfully in a design, so we adopted it wholesale. Now that we have a board that works, we can try other arrangements like that. I can simulate it an add it to the final article tomorrow.

      • SQKYbeaver says:

        i was going to use a similar setup on my bench power supply,

        i like the adjustable voltage references ic the work well in these situations.

      • bearmos says:

        since the OPA2830 is a dual op-amp, you could simply setup the second (unused) channel as a buffer and put the voltage divider on it’s input, feeding the output to R34 and doing away with everything “underneath” R34 in the schematic above.

      • bearmos makes a very good point

      • PapaD says:

        1) Looks like T1 is wired in the emitter-follower configuration so its acting like a buffer. Its buffering the DC offset voltage so that R8 resistance will not mess with the opamp feedback resistors and therefore unintentionally change the gain of the opamp.
        2) Also, I agree with bearmos.
        3) Having only just come across this site I’m not sure if this is the complete front end? if it is then the parallel resistance formed by the input potential divider will cause impedance matching problems at higher frequencies. At lower frequencies the high impedance will not load your input signal much so I guess its a trade off.
        4) If I may offer some advice, for increasing input impedance, it would be to tweak your input circuit so that the input signal first goes through a series capacitor (since you don’t want DC coupling) to remove any potential DC offset on the input (which will superimpose on top of the DC offset you have set via R8). The capacitor feeds the signal to a load resistor. The other side of the load resistor connects to the centre of a potential divider network designed to bias a transistor at its mid point. The signal continues from the capacitor, past the load resistor then into the base of an emitter follower whose emitter junction is ‘bootstrapped’ to the potential divider midpoint. (See
        as Wikipedia has a very complicated example). The emitter follower output can now go to your potential divider & opamp or ADC driver chip (recommended). The result is a massive increase in your input impedance which means you no longer load your input signal.
        5) You may wish to ignore 4 and simply replace all of your circuit with and AC coupled emitter follower in which the signal is attenuated by the input potential divider circuit that simultaneously biases the emitter follower to 2.5V or what ever you set with R8.

  2. SQKYbeaver says:

    there are many ways to accomplish an voltage offset. searching for the most linear and cleanest can be difficult.

    been thinking about building an op-amp test-board for standard pin-out parts with various configurations.

  3. tinito says:

    Ian, what do you use to generate those plots? (I mean the one showing the signal at different stages)

    • Ian says:

      They are made in the open source dia program, it is a vector graphics business diagramming app. There is a microsoft equivalent, but I’ve never used it and don’t know what it is called.

      The new graphic replaces my hand-drawn sketch that was up earlier :)

      • tinito says:

        Ok, DIA again. I will have a look, it is years that I hear about it but i’ve never used it (I’m a gnuplot fan but some stuff cannot be done with gnuplot alone).

        I loved your hand-drawn sketch, anyway ;D

        Thanks for sharing!

      • Ian says:

        I jsut wanted to add that the source for all our artwork eventually ends up in the /art/ folder of the source download and SVN.

  4. Steve says:

    I just wanted to say how much I’ve enjoyed reading this series on the DSO design. Great stuff… more like this please!

  5. mossmann says:

    Have you considered using an ADC Driver IC? You could accomplish all this and perhaps more (single-ended to differential conversion, programmable attenuation, low pass filtering) with the right part.

  6. pali says:

    nice description!
    an overvoltage protection (zener) diode sholdn’t be connected between the ADCs inputs?

  7. JanW says:

    The transistor is used as a current source/current amplifier. The opamp circuit is of very low impedance, which means the bias voltage source has to supply a lot of current (up to tens of mA). A simple voltage divider would on the first hand eat a lot of quiescent current and on the second hand the bias voltage would be modulated by the current draw.


    • Ian says:

      I’ve looked at the flashy boards before. I can’t download the PDF right now for some reason, but as I recall it doesn’t actually show a schematic or partlist. They seem to go to great lengths to obfuscate the design unless you buy it, then I guess you get the schematics on a CD or something.

  8. bonybrown says:

    The problem with using the pot directly between R34 and R33 is that when you adjust the voltage offset, you will also be adjusting the ratio of the voltage divider between the op-amp output and the inverting input. This will alter the gain.
    In this design it wouldn’t matter though, as you can compensate for the gain change by trimming the pot on the non-inverting input.
    Just remember to do the offset adjustment first (with input grounded), THEN the gain (R12) adjustment, otherwise you’ll be chasing your tail!
    So the purpose of T1, C20 and C4 is to provide a low-impedance DC voltage source. The offset voltage can change, without changing the gain. As others have noted, you could use another, very low spec, op-amp to replace most of the T1 and associated circuitry. A voltage reference (zener or something else) might be useful to ensure it remains stable in the face of supply voltage changes.

  9. Don’t add banana plugs if you are going for even a 10MHz sample rate. If the user is novice enough that they don’t have a probe around, they’re definitely too novice to know what using banana leads will do to their high bandwidth signal. Including banana jacks would be bad from a protect-the-user-from-himself perspective.

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