App note: D-PHY Solutions

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An app note (PDF!) from Xilinx on D-PHY Solutions:

Traditionally, interfaces between components on a printed circuit board (PCB) are based on single-ended parallel buses at low bit rates (LVCMOS), differential high-speed serial buses, or single differential channels.
The D-PHY provides an extension to this structure by turning the low-speed, low-power interface to the serial format of the high-speed differential interface, so that both are combined into a single serial interface. With this method, the D-PHY provides a flexible high-speed differential and low-speed, low-power single ended serial interface solution for interconnection between components within one product.
The D-PHY specification is written for ASSP devices or ASIC implementations in mind.
It includes and combines SLVS (high-speed) and LVCMOS (low-power) I/O into a single differential pair of wires (see Figure 1) and as previously mentioned FPGAs do not yet support native D-PHY-compliant I/O.

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