When you get your CPLD development board, you’ll want to start coding! Programs for Xilinx CPLDs are most commonly written in Verilog or VHDL, and you will find examples on our CPLD page. A third way which is usually easier for beginners is schematic entry which you can do in the free Xilinx ISE WebPack. […]
Tag Archives: Xilinx
Xilinx releases ISE Design Suite 13
Xilinx has released version 13.1 of their ISE Design Suite. including a number of new features. This software is used to develop programs from Xilinx CPLD and FPGA products, including the CoolRunner-II chips found in our development boards. The suite includes the free Webpack ISE. Note that this is a ~4 GB download. However, Xilinx […]
Xilinx CPLD applications handbook
This document from Xilinx could easily be titled “Everything You Always Wanted to Know About Xilinx CPLDs But Didn’t Know Where to Look.” Its the Xilinx CPLD Applications Handbook, featuring the CoolRunner-II and XC9500XL. It’s a 422 page compendium of application notes, hardware interfacing tips and specs that any Xilinx CPLD user will want to […]
Xilinx free CPLD/FPGA design handbook
Xilinx has a helpful free publication, the Programmable Logic Design handbook. This quick start guide introduces their line of CPLD and FPGA devices and the basic steps to program development using their ISE Webpack. A listing of application notes and reference designs is included. Download your own copy of this 144 page PDF.
Xilinx XC9500 CPLD docs
Here’s a quick link to the Xilinx library of support documentation for the XC9500 series of CPLDs. Datasheets, user guide, app notes and more!
Xilinx free FPGA/CPLD design tutorials
The Arduino platform and bare microcontrollers are good ways to get started in developing embedded systems. But the way of the future is clearly CPLD and FPGA architecture. These devices are not simply a new type of chip, but a new and interesting design and development frontier. Their programs are developed using several methods, including […]
Small CPU core on a FPGA
Here is the paper James Bowman presented at EuroForth 2010 detailing his project to build a small 16-bit CPU core Forth machine on a Xilinx FPGA. This 200 lines of Verilog code could be helpful to anyone studying FPGA project design. Via Hack a Day
