App note: Active capacitor discharge circuit considerations for FPGAs

Posted on Sunday, May 14th, 2017 in app notes by DP


Power down sequencing and discharging on FPGAs app note from Diodes Incorporated. Link here (PDF)

FPGA’s need the different power rails to be powered up and down in a defined sequence. For power down, each sequenced rail needs to be fully off before the next rail is turned off. With large high speed and high functionality FPGA’s, the power rails have large bulk capacitors to be discharged quickly and safely within a total time of 100ms and up to 10 rails each to be discharged within 10ms.

This application note shows a methodology and considerations for safe open ended shutdown to be controlled by a power sequencing circuit and using correctly chosen MOSFET to discharge the capacitor bank.

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