Another application note from XJTAG on preparing Xilinx FPGA for proper boundary scan testing. Link here When Xilinx FPGAs are configured it can restrict the boundary scan access to some signals on the device. One work-around for this problem is to configure the FPGA with a ‘blank’ image that closely matches its unconfigured state, allowing […]
Tag Archives: XJTAG
App note: Using a test reset section to initialise JTAG devices
An app note from XJTAG about applying test reset to put some devices to JTAG compliant mode. Link here Some JTAG devices require a specific sequence of states to be applied to some signals in order to put the device into a JTAG-compliant mode. This application note describes how a Test Reset section can be […]