Logic analyzer firmware development update

Posted on Tuesday, January 26th, 2010 in logic analyzer by Ian

Today we completed an initial PIC firmware for the open source logic analyzer. The PIC has two operating modes: a serial bridge for SUMP to talk to the client on the FPGA, and a ROM programmer that updates the AT45DB041D flash chip with new logic for the FPGA. There’s still some bugs, but the design is coming together. Give your suggestions and follow our progress in the forum.

Major to dos:

  • Finish the USB bootloader port to 18f24j50
  • Clean and comment the PIC source
  • Clean up the PERL updater scripts
This entry was posted on Tuesday, January 26th, 2010 at 7:48 pm and is filed under logic analyzer. You can follow any responses to this entry through the RSS 2.0 feed. You can skip to the end and leave a response. Pinging is currently not allowed.

3 Responses to “Logic analyzer firmware development update”

  1. Shadyman says:

    I think you win the prize for number-of-simultaenous-gadgets-connected.

  2. Colin I says:

    Ha! There’s only three there and one of them is a breakout board! Whens the last time you’ve tested a new product? My god, I have between 4 – 6 boards connected at any given time! It gets so annoying to manage all those cables!

  3. Ian says:

    Just wait till I get a Saleae Logic on there to figure out the bug!

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