Open source logic analyzer update

Posted on Thursday, December 17th, 2009 in logic analyzer by Ian

A few months ago we started working with the Gadget Factory to build an open source logic analyzer. After a very successful collaboration, we’re almost ready to order the first PCBs. Click here for a large PCB image [PNG].

The draft device has 16 buffered (5volt tolerant) input channels, and 16 unbuffered I/O channels on a wing header.  The PC connection is USB 2.0 with a PIC18F24J50 microcontroller. Both the PIC and the FPGA firmware will be USB upgradable.

You can follow our most recent progress in the forum. Uwe’s block diagram of the final design follows.

Block diagram maintained by Uwe. Click for a large image version [PNG].

This entry was posted on Thursday, December 17th, 2009 at 8:38 am and is filed under logic analyzer. You can follow any responses to this entry through the RSS 2.0 feed. You can skip to the end and leave a response. Pinging is currently not allowed.

7 Responses to “Open source logic analyzer update”

  1. ladyada says:

    count me in for a kit’s worth. ill be a alpha tester :D

  2. Shadyman says:

    Is the Xilinx programmable with the BusPirate via JTAG? :D

  3. Ian says:

    The Bus Pirate JTAG mode is a very low-level state machine navigator that doesn’t really program, but there’s ongoing work to add Bus Pirate support to OpenOCD (the premier open source JTAG programming/debugging app).

    On the other hand, yes! This design stores the FPGA synthesis in a ROM chip. The ROM can be upgraded over the on-board USB interface (PIC chip), but it can also be updated through the header at the top of the PCB (ROM-ISP). The Bus Pirate is a supported FlashRom programmer, so you could use that to update the chip though the header, as well as the Bus Pirate raw SPI mode with a small Perl/Python/etc script.

    In fact, I’m going to ‘steal’ part of the Bus Pirate’s public domain source to make the ROM update interface compatible with Flashrom’s Bus Pirate mode :) The SUMP PUMP will appear as a Bus Pirate to flashrom in upgrade mode.

  4. Shadyman says:

    So how much more awesome is this compared to the BusPirate’s Logic Analyzer mode? I note the 16 (+16) vs 5 channels, how about sample speed? Buffer size?

  5. dan tarr says:

    It looks based on the sump analyzer so should be the same:

  6. Mike Donovan says:

    Suggestion: Add two mounting holes within the ground plane at the right end of the board, to provide some board/case strain relief for the cable header, especially if you use a right-angle header (which would also make it somewhat breadboard-friendly).

    Also, I like the modular repeating design of the riser connectors, do you plan to make different riser half-cards that can be mixed and matched, like maybe a fast 8-bit A/D card? (Should the riser connectors be father apart to accommodate larger half-cards?)

  7. kanchana says:

    Will this kit be available soon . i would like to be one of the first customers

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