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Open source logic analyzer clients

Posted on Monday, September 28th, 2009 in logic analyzer by Ian

sump

Today we played with a few open source logic analyzer clients in preparation for an upcoming prototype. The best we found is SUMP, written in Java. There’s also compatible host software for several FPGA development boards, we found even more ports floating around the web.

SUMP has a SourceForge page, but it doesn’t look very active. Jack Gassett’s ButterFly Platform has a SUMP compile for Windows that doesn’t require you to install the complete Java framework. You’ll also need the rxtx Java library for your platform.

Do you know of any other clients or SUMP resources?

This entry was posted on Monday, September 28th, 2009 at 1:05 pm and is filed under logic analyzer. You can follow any responses to this entry through the RSS 2.0 feed. You can skip to the end and leave a response. Pinging is currently not allowed.

22 Responses to “Open source logic analyzer clients”

  1. ladyada says:

    do you want to make an OS logic analyzer? i have some concrete ideas and would join an effort :)

  2. Ian says:

    Absolutely. I’d eventually like to have a cheap-to-build ($30-$40) FPGA-based LA board with at least 70MHz+ data acq (limited by cheap buffer chips). The main hang up for a simple ‘kit’ is soldering the FPGA chip, which is usually TQFP-something.

    Have you ever looked at the Bitclone design? I once tried to build a CPLD-based LA in the style of the Bitclone, but a modern FPGA is faster, cheaper, easier to work with, and it doesn’t require an external SRAM.

  3. Ian says:

    Sorry, that’s Bitscope: http://www.bitscope.com/design/

    I think it was an old Circuit Cellar publication. I wanted to make an updated version and call it the Bitclone.

  4. ladyada says:

    fpgas are nice but was thinking that perhaps more like the usbee. the ez-usb chips can push thru data at high speed USB rates meaning no on-board buffer – there are some benefits altho the max capture rate is 24mhz :/ on the other hand, 24mhz is pretty fast for most people. and the chips ‘bootload’ from the driver so firmware updates are really ‘ez’.

  5. Ian says:

    Do you have a Usbee, Saleae Logic, or similar? I use the Logic a lot, I really like it. It’s fast enough for 99% of the prototyping work that I do – especially under debug where clock speeds can be reduced. I rarely use it over 1MHz.

    The major downside I’ve found to the ez-usb LAs is USB congestion and latency issues. I’m debugging a USB device right now using the Logic. Between these devices and my keyboard, even attached to different internal USB hubs, I can rarely sustain transfer rates > 0.5mhz (I think it’s latency and not bandwidth).

    Capture LAs seem best for speed, while the EZ-USB is basically a fast logger that can take unlimited samples. In practice I’ve never needed either. Multi-hundred MHz sampling rates are appealing, but like you said, I rarely use > 1mhz. I used to relish the idea of unlimited samples for recording long bus transactions. In reality, I rarely look beyond the first screen of output.

    What the driver situation for the EZ-USb chips? How cross-platform and open is it, and what kind of client would be needed to drive it? I’ve always leaned towards the sampling LA because the data can be pushed through a serial port (or serial->usb FTDI) to any operating system. I avoid desktop programming whenever possible, so having an available multi-platform open client like SUMP has been important.

    I’ve been doodling a variant of the CC Butterfly Platform by Jack Gassett:
    http://gadgetfactory.net/gf/project/butterfly_main/
    He uses an FTDI chip in bit-bang mode to reprogram the FPGA, and then uses the serial->USB part to interface with SUMP. I think it’s a brilliant setup. Boards are available, but the design seems developerie. If you sacrifice some speed, channels, and flexibility, you can probably get a 0-5.5v, 8-16channel ~100MHZ LA with a ton of samples, in the $30 price range.

    It’s all just a thought at the moment. I’m trialing the clients for a related project, not a full-on LA. What’s your thoughts on spoilers? You guys don’t seem to discuss upcoming projects on your blog. I don’t either, but I’m tempted to because it could be another aspect of open and collaborative design. I do put Easter eggs and hints in posts.

  6. ladyada says:

    oh yes, we have all sorts of hints. :D they’re often on flickr, twitter, forums, wiki, weekly chat, etc. srsly, anyone can divine what the next 3 kits are. you just have to look

    personally i dont have a LA, but im actually cool with not owning something i plan to design. that way its fresher. the saelae is (afaict) identical hardware to the usbee. you can dev the ez-usb on linux (ive done it) with sdcc. not saying its the easiest but a single-chip solution has a lot of benefits! OTOH sram is dead cheap. you could use a fast ARM to clock it and do the USB clientin’.

  7. Luke Skaff says:

    @Ian

    I have a Usbee and it is great for protocol decoding and lower speed stuff but it really can not handle high speed and a huge limiter is that it only has eight channels. The Usbee just uses a simple cypress USB peripheral controller (links below) which is easy to design but really not the best thing for a logic analyzer.
    http://www.cypress.com/products/?rpn=CY7C68013A&fid=14
    http://www.cypress.com/?docID=18937

    I would love to see a open and dedicated DIY logic analyzer product, that would be so awesome. A FPGA design would definitely be the way to go and would allow for a much larger number of channel input and higher speeds

  8. Jack Gassett says:

    Hello,

    I just stumbled on this conversation and wanted to put a word in, even if its late. It looks like Ian was already successful in adapting the Bus Pirate to act as a low speed Logic Analyzer.

    I was wondering if you guys have any interest in working towards a full testbench? One of the advantages of the FPGA is that it is pretty easy to adapt it to do other things. It wouldn’t be too much of a stretch to make a Logic Analyzer, Flash Programmer, Oscope, Frequency Generator, and variable Power Supply. All with one device.

    I’ve watched both of your projects over the years and they have been part of what has inspired me to start my own projects. So I would be thrilled to collaborate on something.

    Take care,
    Jack.

  9. Jack Gassett says:

    Actually another possibility occurred to me after I wrote the above. How about if we took my existing FPGA design and streamlined it into an open and DIY Logic Analyzer? We could really bring the cost down by removing the 3.3V power supply, using a cheaper (and faster 480Mb/s) FT2232H chip, and making a single PCB. We could also add improvements such as Voltage Buffers and SRAM.

    We could possibly offer a 100Mhz 32 channel/200Mhz 16 channel Logic Analyzer for $60-70. With the faster FT2232H chip and some SRAM we might even be able to pull off realtime output with fewer channels. And with the Voltage Buffers we could sample signals between -.5 and 7 Volts.

    We could then offer kits and assembled kits in our respective stores.

    Jack.

  10. Ian says:

    Hey Jack,

    I love the Butterfly design, it’s really great. Thanks for commenting!

    The Butterfly has a ton of features, I think there’s a lot of room to ‘strip it down’ into a simpler hobbyist board.

    Do you have a specific buffer in mind? I like the 74F125 because it’s cheap, and pretty fast (5ns, but as I recall it’s good for switching to ~70MHz). I used the f125 in a CPLD LA design that wrote to an SRAM because you can tristate the pins and play the data back without interference from the outside IO source.

    What are you thinking in terms of SRAM? I’ve worked with CPLDs, but I’ve been eyeing the FPGA because it wouldn’t need the external RAM.

    Have you ever check out the Bitscope design? They implement a sampling o-scope with an 8-bit parallel output ADC. I’ve got a ton of chips around for this, but I’m not an analog person so I’ve never completed the design. TI and Maxim both make several different high-speed || output ADCs. Basically, give the ADC a clock source and just feed to output to 8 of the digital channels, slick.

  11. Luke Skaff says:

    I think you would still need external SRAM with a FPGA, at 70Mhz+ with 16-32 channels that would add up to a lot of data quickly. To reduce chip count it would be good to use a octal buffer like the 74F245

  12. Luke Skaff says:

    (I by mistake hit send before I was finished, opps)
    The 74F245 is also a transceiver which would allow you to switch banks of pins to create outputs for a frequency \ clock output, etc.

  13. Ian says:

    Sorry, I pulled those numbers out of thin air. I’ve used the 74-573, it’s octal,, this one to be exact:
    http://www.mouser.com/Search/ProductDetail.aspx?R=74LVT573WMvirtualkey51210000virtualkey512-74LVT573WM

    Here’s my previous dev board for the LA (using the 573): http://hackaday.com/2008/12/11/how-to-programmable-logic-devices-cpld/

  14. Ian says:

    SRAM – How much SRAM can you put inside an FPGA? What’s the benefit of an FPGA over a CPLD and tiny microcontroller in that arrangement?

    As I recall from my previous journey into the world of SRAM, speeds go up to around 100MHz. They are 8,16,32 bits wide, and around 18 address lines for a 4Mbit (256K sample) chip.

    Like: http://www.mouser.com/ProductDetail/Cypress-Semiconductor/CY7C1041D-10ZSXI/?qs=sGAEpiMZZMs6Aik9Fp479rPSFu914cdUmPOXn5OlesE%3d
    9Mbit/166MHz: http://www.mouser.com/ProductDetail/Cypress-Semiconductor/CY7C1360C-166AXI/?qs=sGAEpiMZZMs6Aik9Fp479rPSFu914cdUuGgsK3ZVMt8%3d

    If I were doing this on my own, here’s the things that give me pause. But together we might prevail :)
    That’s a lot of pins to route, with the expectation of high-speed signaling.
    Those are some expensive chips.
    What kind of buffers are fast enough to interface the SRAM at 166Mhz? How much do they cost?
    How much ram is enough? I’m a fairly active prototyper and I never use more than 4K samples (the first screen of output) to debug issues. I have no idea what other use profiles require in terms of storage.

  15. Luke Skaff says:

    You can put a small microcontroller inside a CPLD also, lattice has a free 8-bit micro core and many others offer free cores. A CPLD or FPGA should work fine for this project.

    No buffers are used to interface with SRAM, you wire the RAM directly to the FPGA\CPLD. Sometimes series termination resistors are used to reduce ring. SDRAM or DRAM could also be used.

    The FPGA used in the butterfly only has 216k of dedicated block ram on the device. It would be cheaper to use DRAM instead of SRAM but would need a much more complicated memory controller core on the FPGA, $2-3 for 16Meg: http://www.mouser.com/issi/

    Lots of fun options to choose from, it seems it could be done for less then $75 sales price for hardware

  16. Ian says:

    @ Luke – it sounds like you propose using the ram to store states taken from other pins in the FPGA or CPLD. That’s way beyond my abilities, we’d have to hear from Jack (unless you’re volunteering). I know propagation delay is a factor.

    DRAM is indeed cheaper, and I understand it’s not difficult to implement a controller in FPGA or CPLD (I’ve read a few nice app sheets). But again, way beyond what I can knock-up in a weekend on a 2-layer board.

    There’s sump host implementations for a bunch of different FPGA DEV boards. My existing plan was to find a good one with highly-available parts, strip it down, and make the cheapest, simplest 2-sided PCB I can. If it floats, and I can stand the dev tools (Xilinx 10.1 was a nightmare), then I’d plan a version 2. My price goal was around $30, shipped, I worry more is on par with a full FPGA dev board.

    If there’s serious interest in collaboration, I’ll start a new board in the forum and we can start looking at parts.

  17. Luke Skaff says:

    Yea, you are right, it would be best to just keep it simple on the first board. If it is popular a version with external ram and greater memory depth could always be made after the proof of concept.

    I designed a DRAM controller for a project in school but that was some time ago. Opencores has a few memory controllers you can just drop into the design. Also many of the FPGA/CPLD vendors offer free memory controllers you can integrate into your design, the learning curve is not bad but it is definitely time consuming.

  18. Jack Gassett says:

    Hello,

    I think we should try to make it as simple and cost effective as possible for the first revision. The Spartan 3E-250 has 216k of block ram which would give us 6K samples. For most purposes that is enough… We could easily drop in a Spartan 3E-500 which would give us 11k samples at 32 channels. We can also try to use distributed ram or only provide 16 channels if we really want to provide more samples. So for the first revision I would suggest we forgo the SRAM, SDRAM, or DRAM. I’ve made designs with SDRAM and DRAM in the past with mixed results. I was never able to get DRAM to work properly with a double layer board. SDRAM is possible on a two layer board but I think we should save that for a later revision. I think most people will be very happy with 6K samples. I only mentioned SDRAM because I think that will be the key to making it function in realtime…

    So if you guys agree to forgo the external memory then that leaves the question of providing a voltage buffer for the inputs. Do you feel it is important? The Spartan 3E can handle up to 3.3V by itself but will be damaged by anything higher. I have a buffer design in place already, http://www.gadgetfactory.net/gf/project/bpw5009-buffer/ based on the 16 bit M74LCX16245. This would allow voltages up to 7V and is 4.5ns and would require only two parts.

    I’m down for collaborating on this, but I’m not sure we could accomplish a sale price of $30… The spartan 3e chip is $13 and the ftdi2232h is $4 or $5… The power supply will probably add $3-6. PCB will cost $2-4. These numbers are off the top of my head and might be off.

    Jack.

  19. Jack Gassett says:

    You know, we might be able to pull off $30-40 sale price if we use linear regulators and eliminate the USB chip in favor of a max232 chip.

    Jack.

    • Luke Skaff says:

      @Jack,

      I obviously can’t speak for others but I would be willing to pay extra to have full USB 2.0 speed with a FT2232H. I think having the ability to stream data a few Mhz and lower to your PC would be worth the extra few dollars.

  20. Ian says:

    I started a forum to continue this discussion, if there’s interest:
    http://whereisian.com/forum/index.php?board=23.0

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