App note: Power supply rejection for low-jitter clocks


Method of rejecting noises from power supply, an app note from Silicon Labs. Link here (PDF)

Hardware designers are routinely challenged to increase functional density while shrinking the overall PCB footprint of each new design. One significant challenge is minimizing clock jitter through careful board design while meeting the design’s functional and space requirements. Since jitter is a measure of signal fidelity, it requires an understanding of diverse analog concepts, such as transmission line theory, interference, bandwidth, and noise, in order to manage their impact on performance. Among these, density impacts sensitivity to external noise and interference the most. Since noise and interference are everywhere and since multiple components share a common power supply, the power supply is a direct path for noise and interference to impact the jitter performance of each device. Therefore, achieving the lowest clocking jitter requires careful management of the power supply. Sensitivity to power supply is commonly referred to as power supply ripple rejection or power supply rejection ratio (PSRR). For jitter, ripple rejection is more appropriate.

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  1. This is a venerable SiLabs App-Note (c.2013). As someone who deals with RF/Microwave systems, I regularly run into compromised expected BER vs. S/N (etc., etc.) problems in production products. Most often the problems are caused by lack of attention to noise in the power subsystems and bad board and ground subsystem layout. At my post-time SiLabs seems to be one of the the last hold-outs against the “Buy-Out/Consolidation” frenzy in the semiconductor industry over the past few years. SiLabs still seems to SiLabs. Yay! :-)

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