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MSP430 Launchpad Logic Analyzer based on the Logic Shrimp

Posted on Thursday, July 5th, 2012 in Logic Shrimp, MSP430 by DP

oPossum built a 6 channel logic analyzer booster pack for the MSP430 Launchpad. His design is inspired by the Logic Shrimp and used SPI serial interface RAM chips to store samples. The MSP430 software is SUMP compatible and works with Jawi’s OLS client.

This is a logic analyzer add-on for the TI MSP430 Launchpad. It is inspired by the Logic Shrimp – you could say it is a rip off the design – that would be quite fair.

There are a few differences in the design compared to the Logic Shrimp.

The SPI RAM chips have the SI and SO lines tied together. This reduces the pin count needed on the microcontroller…

The MSP430 can output it’s internal clock on P1.4, so this is used to clock the SPI RAM during acquisition. This feature eliminates the need for a tristate buffer between the oscillator and RAM CLK line…

With the Scanalogic 2, there are now designs for SPI SRAM-based logic analyzers for AVR, MSP430, and PICs.

This entry was posted on Thursday, July 5th, 2012 at 7:00 pm and is filed under Logic Shrimp, MSP430. You can follow any responses to this entry through the RSS 2.0 feed. You can skip to the end and leave a response. Pinging is currently not allowed.

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