App note: Power supply rejection for low-jitter clocks

Method of rejecting noises from power supply, an app note from Silicon Labs. Link here (PDF) Hardware designers are routinely challenged to increase functional density while shrinking the overall PCB footprint of each new design. One significant challenge is minimizing clock jitter through careful board design while meeting the design’s functional and space requirements. Since […]

App note: Noise sources in low dropout (LDO) regulators

Looking for a clean power supply for a sensitive analog circuit? Analog Devices describes the sources of noise in LDO voltage regulators, and provides some examples to limit and combat the noise. In general, LDO noise comprises two components: intrinsic, or internally generated noise, and extrinsic, or externally generated noise. Thermal and 1/f noise are […]