App note from International Rectifier on how to optimize the maximum current handling of power FETs. Link here (PDF)
There is a trend within the discrete power component industry of late to increase the dc current rating for low on-resistance devices to levels that historically have not been seen. This trend has accelerated as power transistor manufacturers introduce higher current / lower voltage designs. Mature JEDEC package designs, originally intended decades ago for dc currents on the order of 10’s of Amperes are now emerging as capable of 100’s of Amps. Is this due to some significant improvement in package materials / design or is this all smoke and mirrors? The answer is a little of both.