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App note: Trends in integrated circuits that affect ESD protection requirements

Posted on Sunday, June 17th, 2018 in app notes by DP

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A quick lookup on the ESD protection evolution of ICs in this app note from ON Semiconductor. Link here (PDF)

The stunning progress in integrated circuit capability over the last 40 years is most succinctly expressed by Moore’s Law; “Every 2 years the number of transistors that can be economically manufactured in an integrated circuit will double”. The secret to this success has been the shrinking of integrated circuit feature sizes in all three dimensions. To maintain circuit reliability with the smaller dimensions the operating voltage of integrated circuits has been steadily declining. This trend will continue in the future, as documented in the International Technology Roadmap for Semiconductors. As the working voltage for integrated circuits decreases the voltage at which circuit damage can occur also decreases.

The move to smaller geometries has also prompted fundamental changes in IC technologies that have had an adverse effect on the intrinsic ability of the technologies to survive ESD stress. A prime example is the evolution of nMOS transistors in CMOS technologies.

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