7400 competition entry: I2S DAC with a Class D amplifier output

This I2S DAC with a Class D amplifier output has been entered into the open 7400 competition. It uses a mix of 74HCxx and 4000 CMOS series logic ICs to achieve the desired result.

My last minute entry to the 7400 series logic competition. I’m using a SN74HC132 hex NAND gate, a CD4094BE 8 bit shift register, two CD4585BE 4 bit comparators, a SN74HC590 8 bit counter, and a SN74HCU04 hex inverter. The i2s data and clocks are used to generate a PWM signal by comparing the data with counter values. The output from the comparators is used to drive a class D amp.

This ended up being more of a proof of concept, as I ran out of time to debug everything. There are some bugs that need to be worked out, but I didn’t have any logic analyzer to debug the 8 bit bus. However, the frequency sweep shows everything working for the most part!

Check out the video after the break.

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