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3D Model: Logic Shrimp v2b

Posted on Monday, October 15th, 2012 in 3D Model, Logic Shrimp by DP

Today’s 3D model is the Logic Shrimp v2b. The newer version uses the single 23LC1024 SRAM instead of four 23K256, and the serial data lines (SD0 – SD3) are now bi-directional.

The Logic Shrimp is a 4 channel, medium speed, low cost logic analyzer with 256K samples and 20MHz top speed.

Check out our tutorial on how to build 3D models from Cadsoft Eagle board files, as well as the tutorial on how to render life like images with Kerkythea.

The models will be published in the Dangerous Prototypes 3D warehouse collection. They are also uploaded to our SVN. You can find them inside the “art” folders in the respective project folders.

Get the version 1 for $34.90 at Seeed Studio.

This entry was posted on Monday, October 15th, 2012 at 5:00 pm and is filed under 3D Model, Logic Shrimp. You can follow any responses to this entry through the RSS 2.0 feed. You can skip to the end and leave a response. Pinging is currently not allowed.

4 Responses to “3D Model: Logic Shrimp v2b”

  1. Enlightenment says:

    Seriously, you change to just one chip. When I read some past blog entry that you were changing the board to support the 23LC1024, I thought surely it would have 4 times more memory. Yawn!

    • Ian says:

      It’s part of my personal goal to make a cheap and usable DIY logic analyzer available to everyone. I’ve been stabbing at it for years. Eliminating 3 SRAMs greatly improves the layout. The board and shape is case friendly and less noisy.

      I’m also totally fascinated by all the different topologies out there for recording digital logic, this one is super cool, I love the concept.

      As it is, the Logic Shrimp has the max memory supported by the client and protocol :) Not that we can’t update that in the future :) a version with more memory may be in the future

    • Hardcore says:

      4 times more memory?

      If you want a really fast logic analyzer you can build one yourself, go out buy some static rams link the I/O pins as the inputs, then just use a high-speed counter and toggle the R/W line/ CS/ select at the speed you want to sample.

      Then to read the sample just reverse R/W line and buffer the data out and decode it.
      More width, just add more devices, I bet you could have it breadboarded in a day, hay it might even make a good design for the 7400 competition.

  2. hmm to me 4 ram chips would have meant interleaving, and 4x more bandwidth!

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