Open 7400 prize: DE0-Nano development kit from Terasic

Posted on Wednesday, October 3rd, 2012 in 7400 contest, contest by DP

Terasic donated a DE0-Nano development kit to the Open 7400 Competition.  Get your entry in and this and other cool hardware can be yours.

The DE0-Nano board introduces a compact-sized FPGA development platform suited for prototyping circuit designs such as robots and “portable” projects. The board is designed to be used in the simplest possible implementation targeting the Cyclone IV device up to 22,320 LEs.

Thank you to Terasic for sponsoring the 2012 Open 7400 Logic Competition!

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5 Responses to “Open 7400 prize: DE0-Nano development kit from Terasic”

  1. neslekkim says:

    How is the capacity on this fpga compared the Spartan 3E500?, or the Spartan 6 LX9?, I’m not that into understanding all those numbers yet, but 3e is like 500K gates, LX9 is similar in size, and this have.. 22K logic elements?

  2. philwatcher says:

    check this page:
    I have both a Spartan 3A200 and the DE0 Nano and the DE0 just blows the same-priced spartans out of the water.
    3E500k has ~9k logic cells, 360k Block RAM, 20 Multipliers @ 250MHz
    Cyclone IV has ~220k logic cells, 600k block RAM, 66 Multipliers @ 280MHz
    Also, the Spartan 3 DCM is rather limited (1..32 mutiplier/divider, with maximum frequency of 333MHz internally), whereas the Cyclone IV PLL goes to 1300MHz internally, and I have used multipliers/dividers > 200.
    Finally, Quartus (Altera) comes with the free SignalTap Logic analyzer.
    However, the ISE (Xilinx) IP cores available are free (vs. 1-hour time limit with Altera).
    Spartan 6: they are better than Spartan 3 (duh) and come with a PLL, though the cheapest Spartan 6 boards that I was able to find were still 30% more expensive than the DE0.

    • Mikkelsen says:

      Reason for bringing in the old spartan 3 is because i have the Papilio One 500k card, and only that to compare with.
      So it seems like this de0 card can be of interrest for toying around with, but what exactly does that 1 hour time limit mean for practical use?, the various cores available for spartan is, as i understand it, available as vhdl/verilog, so one synthesises the bit file for upload, I guess it’s similar for the altera, but do you get time limit on that?

      The creator of Papilio is working on an spartan6 board, but due to manufacturing etc, he is not using the bga versions, so one are abit restricted on the chip choice.
      It does exist another version, pipistrello, but no price/availabilit as of yet:
      And then one have this project, which seems to be very quiet recently:

      what i find interresting about the fpga’s so far is that for hobby use, you can emulate faster/bigger/better arduino-type cores, and have somewhat code compability, one can upload arcadecores for playing, and so on, but these are a bit small if one want to try some multicore things (as far as I have understood so far)

  3. philwatcher says:

    The 1 hour deal is that if you don’t have an Altera “Opencores Plus” license, you can a) not create a .pof file (file for FPGA boot rom) and b) all “evaluated” IP cores force their outputs low after one hour.
    This IP is more advanced stuff like FFT/NCO/whatnot. PLL/RAM instantiation is of course free. If you don’t need advanced IP or use some from OpenCores (the FOSS stuff, has nothing to do with the Altera proprietary stuff), then that is obviously not a problem. It is just that Xilinx offers a lazier way to do it.

    I have been following Pipistrello now for some time, as it seems like an interesting board to me (HDMI). Also interesting are the XuLA2 as well as the ZTEX boards, both Spartan 6, both ~$120.
    Still, I lost interest in all of these when I was able to get the DE0 nano wich brings ridiculous amounts of power and features to the table, in a nice small package. I am not trying to advertise these, I just like mine :)

    About Soft-Arduino – yeah, I have thought about it, but it does take a lot of space. Sure, you would have a 100+MIPS Arduino with extreme flexibility, but you have to speak VHDL as well as C to use the advantages of a softcore. However, if you want a softcore, Altera offers the Nios II (economy version is free) including a complete eclipse-based toolchain and debugging over JTAG. It is, however, relatively large.

    I like the massive high-speed IO that FPGAs offer, and the fct that you can write your own “peripherals” for each port. Definitely not as convenient as a, but definitely more powerful.

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