Dangerous DSO part 1: There’s so much between 0 and 1

Dangerous DSO is a new logic analyzer/oscilloscope prototype we’ve been using in the lab. It combines a 16 channel logic analyzer and one 50MHz oscilloscope channel with +/-10volt DC range. The combined tool shows what your signal does between 0 and 1, which helps pinpoint noise and other electrical glitches.

Our goal with the D-DSO is to make the simplest possible oscilloscope reference design. It doesn’t have range selection or AC coupling, it can’t trigger based on analog voltage levels. It’s a basic design with the bare minimum needed to capture an analog signal.

This screenshot shows the D-DSO view of a pulse-width modulator square wave. The analog view shows that the signal isn’t perfectly square, it bounces around slightly. We haven’t compared it to a real scope yet. There’s no telling what noise is real, and what comes from our crappy analog design.

A general overview of the design follows the break. Daily articles will cover the ADC, the analog front-end, and simulating the circuit all week.

This is not a finished project, it will not be produced. We’re posting an internal design to get some feedback. Look for a new Dangerous DSO article every day this week.

Schematic, PCB, partlist

See the Dangerous DSO wiki page.

FPGA

The Dangerous DSO uses a Xilinx Spartan XC3S250E-TQ144 FPGA. We got really comfortable working with this chip and supporting it on the Logic Sniffer. We could have used the 100pin package, but the pinout on the 144pin version is a lot easier to work with.

The FPGA has a basic support circuit with a 50MHz crystal and various pullup resistors. A 2Mbit flash ROM stores the firmware that the FPGA loads at start-up. We added a button for whatever.

PIC

Our favorite PIC 18F24J50 tends to the ROM programming and USB connection. This is one of Microchip’s featured 3.3volt chips with extended support. It should have good availability for a long time. The PIC runs Honken’s open source USB stack with only a couple issues.

ROM upgrade mode is based around the SUMP protocol. The metadata command 0×04 that returns the hardware description in normal mode also works in update mode. If you try to do a logic capture while the hardware is in update mode the descriptor is different and the client can warn the user. Similarly, the upgrade application understand the normal logic analyzer mode metadata and prompts the user to enter update mode and try again.

The upgrade application has raw access to the ROM chip using Bus Pirate SPI bulk read/write commands. This means new ROM chips can be supported by a software update alone, no firmware changes needed. Bulky chip ID and write algorithms are all in the computer app where they belong.

IO

D-DSO has 16 digital IO channels. 8 are buffered and 5volt tolerant. The buffer is bi-directional, and the FPGA is wired to control the direction and output enable signals.

assign bufferOEOut=1'b0;//OE low for normal outputs
assign bufferDirectionOut=1'b0;//direction low for B->A (external to FPGA)

We modified the latest Demon Core Verilog logic analyzer engine to configure the buffer for input and enable it permanently.

//DSO LEDs
assign groupLEDs[2:0]=disabledGroups[2:0];
assign extClockLEDnn=!extClock_mode;

Each IO group and the DSO input have a LED that lights when they are selected. Group LEDs are controlled by wiring the output pins to the disabled group configuration bits in core.v.

The external clock LED is controlled by the external clock mode bit, also in core.v. We haven’t figured out where to connect the external trigger LED, but that’s ok because we never use it.

Analog

An ADS830 flash ADC measures a voltage and outputs the value on 8 parallel pins. A simple analog front-end with a single opamp gives the ADC a +/-10volts input range.

//DSO clock, range output
assign ADCClockOut=!clock;
assign ADCRangeOut=1'b1;

The ADC needs a clock, up to 60MHz. We make it simple and wired the ADC clock to the inverse of the system clock. A better method is probably needed.

Amazingly that’s the only real change to support the ADC. 8bits from the ADC output pins connect to logic analyzer channel group 3. The FPGA doesn’t care what the data is, it just passes it to the client. Luck for us, the client already has support for displaying a channel group as an analog signal.

All week we’ll post details about the analog design:

1. Feed and water your ADC
2. Messing with your front-end
3. Lets get over simulated

Power

USB and external power supplies are toggled with a switch. USB supplies are not guaranteed to be 5volts, and the fuse eats a little more too. An external supply is more reliable.

We haven’t finished populating the power section, we’ve only used it with the USB supply.

Using it

SUMP clients, even the old ones, already support an oscilloscope mode. Choose scope mode for channel 3 under Diagram->mode settings.

We connected GROUP0 channel 0 and the DSO input to a 50kHz square wave generated by the Bus Pirate. Capture is configured for group 0 and group 3, group 3 is where the ADC data output is attached to the FPGA. Click capture.

There it is, the shades of gray we’ve been missing, our analog hello world. It’s probably a horrible representation of the actual signal, but you gotta start somewhere.

Files

Design files will be available later in the week under a CC BY-SA license. We’ll release a patch against the Demon core eventually, but the snippets here give the general idea.

Get one

You can’t. This is just for fun.

PCBs will be available in the free PCB drawer soon, but beware many issues. VR4 is not connected to ground. The op-amp footprint needs a ton of jumpers and modifications depending on the opamp. The single-turn pots are a terrible choice and make adjustment nearly impossible. More bug discussions later this week too.

Followups

All week we’ll post details about the analog design:

1. Feed and water your ADC
2. Messing with your front-end
3. Lets get over simulated

This entry was posted in FPGA, oscilloscope, Prototypes.