Development of the open source logic analyzer, first discussed here, has progressed rapidly in the forum. We’ve looked at cost estimates, Uwe made some excellent block diagrams, and Jack has already added a basic layout to his SVN. Read our goals and specs after the break.
Tag Archives: logic analyzer
Bus Pirate logic analyzer mode
See the latest version on the documentation wiki. This is an updated guide to the Bus Pirate logic analyzer mode, it expands on the initial documentation posted earlier. Bus Pirate firmware v3.0 introduced a logic analyzer mode that works with the SUMP open source logic analyzer client. The logic analyzer can record 4096 samples at […]
Bus Pirate logic analyzer firmware
We wanted to check the remote control output while we debugged the color changing pumpkin. Usually we’d use a Saleae Logic, but instead we made an experimental logic analyzer firmware for the Bus Pirate. ***BIG WARNING*** The Bus Pirate will never be a substitute for a ‘proper’ logic analyzer, the hardware isn’t designed for it. […]
Open source logic analyzer clients
Today we played with a few open source logic analyzer clients in preparation for an upcoming prototype. The best we found is SUMP, written in Java. There’s also compatible host software for several FPGA development boards, we found even more ports floating around the web. SUMP has a SourceForge page, but it doesn’t look very […]