Here is some basic information about special CPLD pin functions you might need when getting started with Xilinx or any other CPLD:
Global Clock (GCK) pins
Many high-speed digital logic designs need a clock signal that reaches all components simultaneously. While any CPLD pin can input a clock signal and distribute it to the design, GCK pins and their internal connections are optimized for clock signals. They are designed to have minimum skew rates, and that all the connection lengths are the same to allow for perfect synchronicity between devices.
Global Set/Reset (GST) pins
When designing projects that use flip-flops it may be necessary to reset all of them simultaneously. The Global Set/Reset (GST) pins are designed for this purpose.
Global tri-state (GTS) pins
The GTS pin is optimized to toggle all the other pins between input and output. This is helpful if you need to disable all the CPLD outputs at once.
I think there is something wrong with the wording.
“Many high-speed digital logic designs on a clock signal that reaches all components simultaneously.”
“….logic designs rely on a clock…..”?
Fixed, thanks!