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App note: CPLD special function pins

Posted on Saturday, November 5th, 2011 in app notes by DP

Here is some basic information about special CPLD pin functions you might need when getting started with Xilinx or any other CPLD:

Global Clock (GCK) pins

Many high-speed digital logic designs need a clock signal that reaches all components simultaneously. While any CPLD pin can input a clock signal and distribute it to the design, GCK pins and their internal connections are optimized for clock signals. They are designed to have minimum skew rates, and that all the connection lengths are the same to allow for perfect synchronicity between devices.

Global Set/Reset (GST) pins

When designing projects that use flip-flops it may be necessary to reset all of them simultaneously. The Global Set/Reset (GST) pins are designed for this purpose.

Global tri-state (GTS) pins

The GTS pin is optimized to toggle all the other pins between input and output. This is helpful if you need to disable all the CPLD outputs at once.

This entry was posted on Saturday, November 5th, 2011 at 9:00 pm and is filed under app notes. You can follow any responses to this entry through the RSS 2.0 feed. You can skip to the end and leave a response. Pinging is currently not allowed.

3 Responses to “App note: CPLD special function pins”

  1. someonecool says:

    I think there is something wrong with the wording.

    “Many high-speed digital logic designs on a clock signal that reaches all components simultaneously.”

  2. Rohit de Sa says:

    “….logic designs rely on a clock…..”?

  3. Ian says:

    Fixed, thanks!

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