d18c7db was inspired by Markus’ SID audio file player so he implemented a SID player in VHDL:
I spent some time this weekend and got some initial sounds out of my board. I’m using a Papilio FPGA board with a SID core written in VHDL. The sounds coming out sound 90% correct, the tunes are definitely recognizable :) but it’s early days, I still need to fix a bunch of things.
Via the forum.