I2C-bus utilized on several meters of nodes describe and applied in this app note from NXP Semiconductors. Link here (PDF)
The availability of powerful I2C-bus buffers that drive their I/Os on both sides to a nominal ground or ‘zero offset’ logic level allows the removal of noise introduced into one section of a very large bus system. That ‘regeneration’ of clean I2C signals enables building very long I2C buses by combining together relatively short bus sections, each say less than 15 meters, using such buffers or multiplexers.
Conventional twisted-pair communication cabling with its convenient connectors, and a ‘modular’ I2C-bus system approach, make very large I2C systems such as for solar panel array control or multi-storey car parks to indicate free spaces by overhead red/green indicators very simple to construct. Together with the clever PCA9674/A GPIOs with their >100 simple addresses this arrangement could provide competition for RS-485 or other bus systems that cannot equal the number of simply addressable nodes possible in the system as described in the application note. It can be thousands of nodes.
Because very large numbers of buffers, and the wiring, will introduce signal delays that can ‘skew’ the timing of the I2C-bus clock and data signals it becomes necessary to modify the timing margins generated by the conventional I2C-bus components used in small systems.